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oh
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parallella
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fpga
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parallella_timing.xdc
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Fixing typos
2015-11-06 22:40:59 -05:00
create_clock -period 3.333 -name rxi_lclk_p -waveform {0.000 1.666} [get_ports rxi_lclk_p]
Adding parallella synthesis scripts
2015-11-06 06:58:14 -05:00
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