oh/README.md

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# OH!

An Open Hardware Library for Chip and FPGA designers written in Verilog

## CONTENT

| Spec                | Description                                 |
|---------------------|---------------------------------------------|
| [common](common)    | Common utility HW modules and scripts       |
| [edma](edma)        | DMA module                                  |
| [emesh](emesh)      | Epiphany emesh related circuits             |
| [elink](elink)      | Epiphany point to point LVDS link           |
| [emailbox](emailbox)| Simple mailbox with interrupt output        |
| [emmu](emmu)        | Simple memory transaction translation unit  |
| [etrace](etrace)    | Simple logic analyzer                       |
| [memory](memory)    | Various simple memory structures (RAM/FIFO) |
| [xilibs](xilibs)    | Simulation modules for Xilinx primitives    |

## LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE) 

## CONTRIBUTING
Instructions for contributing can be found [HERE](CONTRIBUTING.md).

## RECOMMEND TOOLS

* [Verilator Simulator](http://www.veripool.org/wiki/verilator)
* [Emacs Verilog Mode](http://www.veripool.org/wiki/verilog-mode)
* [Icarus Simulator](http://iverilog.icarus.com)
* [GTKWave](http://gtkwave.sourceforge.net)
* [Verilog-Perl](http://www.veripool.org/wiki/verilog-perl)

## RECOMMENDED READING

* [Verilog Quick Reference](verilog/verilog_reference.md)
* [Sunburst Design Verilog Papers](http://www.sunburst-design.com/papers)
* [Sutherland Verilog Papers](http://www.sutherland-hdl.com/papers.html)