2016-02-24 20:29:56 -05:00
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//#######################################################
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//# Target specific IO logic (fast, timing sensitive)
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//#######################################################
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module mtx_io (/*AUTOARG*/
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// Outputs
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tx_packet, tx_access,
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// Inputs
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nreset, clk, io_access, io_packet, tx_wait
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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2016-02-26 22:51:35 -05:00
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parameter MIOW = 16;
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2016-02-24 20:29:56 -05:00
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//RESET
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input nreset; // async active low reset
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input clk; // clock from divider
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//Core side
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input io_access; // valid packet
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input [2*MIOW-1:0] io_packet; // packet
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//IO interface
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output [MIOW-1:0] tx_packet; // data for IO
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output tx_access; // access signal for IO
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input tx_wait; // pushback from IO
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//regs
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2016-02-26 22:51:35 -05:00
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reg [2*MIOW-1:0] packet_reg;
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reg [MIOW-1:0] packet_sh;
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reg tx_access;
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//########################################
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//# RESET
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//########################################
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//synchronize reset to rx_clk
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oh_rsync oh_rsync(.nrst_out (io_nreset),
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.clk (clk),
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.nrst_in (nreset));
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//########################################
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//# ACCESS (SDR)
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//########################################
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always @ (posedge clk or negedge io_nreset)
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if(!io_nreset)
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tx_access <= 1'b0;
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else if(~tx_wait)
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tx_access <= io_access;
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//########################################
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//# DATA (DDR)
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//########################################
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2016-02-26 22:51:35 -05:00
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oh_oddr#(.DW(MIOW))
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data_oddr (.out (tx_packet[MIOW-1:0]),
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.clk (clk),
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.ce (io_access & ~tx_wait),
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.din1 (io_packet[MIOW-1:0]),
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.din2 (io_packet[2*MIOW-1:MIOW])
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);
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2016-02-26 22:51:35 -05:00
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endmodule // mtx_io
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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