oh/asiclib/hdl/asic_decap.v

//#############################################################################
//# Function: Decap Cell                                                      #
//# Copyright: OH Project Authors. ALl rights Reserved.                       #
//# License:  MIT (see LICENSE file in OH repository)                         #
//#############################################################################

module asic_decap #(parameter PROP = "DEFAULT")   (
    input  vss,
    output vdd
    );

endmodule
Adding asiclib -Represent set of cells that need hard coded cells or hard coded gate level designs. 2021-07-27 22:24:40 -04:00			`//#############################################################################`
			`//# Function: Decap Cell #`
			`//# Copyright: OH Project Authors. ALl rights Reserved. #`
			`//# License: MIT (see LICENSE file in OH repository) #`
			`//#############################################################################`

Adding default property to all cells -Can be used to select between different cells (like sizes) that have the exact same logical function 2021-07-27 22:55:45 -04:00			`module asic_decap #(parameter PROP = "DEFAULT") (`
Adding asiclib -Represent set of cells that need hard coded cells or hard coded gate level designs. 2021-07-27 22:24:40 -04:00			`input vss,`
			`output vdd`
			`);`

			`endmodule`