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oh/elink/hdl/erx.v

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Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
module erx (/*AUTOARG*/
// Outputs
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
Reset timing optimization - holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
2015-10-08 10:34:59 -04:00
rxrr_packet, erx_cfg_wait, rx_lclk_div4, erx_reset, timeout,
mailbox_full, mailbox_not_empty,
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
// Inputs
Reset timing optimization - holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
2015-10-08 10:34:59 -04:00
soft_reset, sys_reset, sys_clk, tx_active, rxi_lclk_p, rxi_lclk_n,
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rxwr_wait,
rxrd_wait, rxrr_wait, erx_cfg_access, erx_cfg_packet
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
);
Adding "ETYPE" as a parameter -set to 0 for parallella -set to 1 for ephycard
2015-09-14 22:03:22 -04:00
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h800;
parameter IOSTD_ELINK = "LVDS_25";
Hard coding for ephycard, may need to fix back later...
2015-09-25 15:21:21 -04:00
parameter ETYPE = 1;
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
//Synched resets, clock
Reset timing optimization - holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
2015-10-08 10:34:59 -04:00
input soft_reset; // sw driven reset
input sys_reset; // async reset
input sys_clk; // system clock for fifo/clocks
input tx_active; // holds rx in check until tx has booted
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
Major RX change: -renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me) -packet interface change -removed wait signals from dataout field -added dma, emmu, mailbox, config register -instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
//FROM IO Pins
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
Major RX change: -renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me) -packet interface change -removed wait signals from dataout field -added dma, emmu, mailbox, config register -instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
//Master write
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//Master read request
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//Slave read response
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
Man that's a lot of yak shaving.... -added register read/write properly -removed redundant wrapper layers in maxi/saxi -changed over to "emesh" interface from packet 103 bit data -cleaned up maxi -cleaned up saxi -removed redundant signals in elink interface (user,lock,..) -added wrapper to fifo (to carry emesh interface through) Now comes the fun part of testing
2015-04-13 23:35:21 -04:00
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
//Configuration Interface (from ETX)
input erx_cfg_access;
input [PW-1:0] erx_cfg_packet;
output erx_cfg_wait;
Reset timing optimization - holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
2015-10-08 10:34:59 -04:00
output rx_lclk_div4;
output erx_reset;
Merge branch 'master' of https://github.com/parallella/oh Adding complete register documentation Conflicts: elink/README.md
2015-04-29 11:55:01 -04:00
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
//Readback timeout (synchronized to sys_c
Added "timeout" to elink interface -Use as error interrupt? -Is there another method for checking error?
2015-04-27 15:11:56 -04:00
output timeout;
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
output mailbox_full;
output mailbox_not_empty;
Added "timeout" to elink interface -Use as error interrupt? -Is there another method for checking error?
2015-04-27 15:11:56 -04:00
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
/*AUTOOUTPUT*/
/*AUTOINPUT*/
Man that's a lot of yak shaving.... -added register read/write properly -removed redundant wrapper layers in maxi/saxi -changed over to "emesh" interface from packet 103 bit data -cleaned up maxi -cleaned up saxi -removed redundant signals in elink interface (user,lock,..) -added wrapper to fifo (to carry emesh interface through) Now comes the fun part of testing
2015-04-13 23:35:21 -04:00
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
Fixing RX reset (again!) -async assert -sync deassert
2015-10-07 20:37:49 -04:00
wire erx_io_reset; // From erx_clocks of erx_clocks.v
wire [44:0] idelay_value; // From erx_core of erx_core.v
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
wire load_taps; // From erx_core of erx_core.v
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
wire rx_access; // From erx_io of erx_io.v
wire rx_burst; // From erx_io of erx_io.v
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
wire rx_clkin; // From erx_io of erx_io.v
wire rx_lclk; // From erx_clocks of erx_clocks.v
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
wire [PW-1:0] rx_packet; // From erx_io of erx_io.v
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
wire rx_rd_wait; // From erx_core of erx_core.v
wire rx_wr_wait; // From erx_core of erx_core.v
wire rxrd_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxrd_fifo_packet; // From erx_core of erx_core.v
wire rxrd_fifo_wait; // From erx_fifo of erx_fifo.v
wire rxrr_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxrr_fifo_packet; // From erx_core of erx_core.v
wire rxrr_fifo_wait; // From erx_fifo of erx_fifo.v
wire rxwr_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxwr_fifo_packet; // From erx_core of erx_core.v
wire rxwr_fifo_wait; // From erx_fifo of erx_fifo.v
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
// End of automatics
Verious silly compilation fixes, nothing to see here..
2014-12-14 22:24:16 -05:00
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
/***********************************************************/
/*CLOCK/RESET */
/***********************************************************/
erx_clocks erx_clocks(/*AUTOINST*/
// Outputs
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.erx_reset (erx_reset),
Fixing RX reset (again!) -async assert -sync deassert
2015-10-07 20:37:49 -04:00
.erx_io_reset (erx_io_reset),
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
// Inputs
.sys_reset (sys_reset),
.soft_reset (soft_reset),
Reset timing optimization - holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
2015-10-08 10:34:59 -04:00
.tx_active (tx_active),
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
.sys_clk (sys_clk),
.rx_clkin (rx_clkin));
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
/***********************************************************/
/*RECEIVER I/O LOGIC */
/***********************************************************/
Bug fixes
2015-06-30 13:32:05 +02:00
defparam erx_io.IOSTD_ELINK=IOSTD_ELINK;
Adding "ETYPE" as a parameter -set to 0 for parallella -set to 1 for ephycard
2015-09-14 22:03:22 -04:00
defparam erx_io.ETYPE=ETYPE;
Fixing RX reset (again!) -async assert -sync deassert
2015-10-07 20:37:49 -04:00
erx_io erx_io (
Reset and clock cleanup -In the default mode we now have 7 input clocks to basic elink -This is too many, need to simplify, not reasonable! -But with all the knobs on the MMCM, performance will be great... -WIP on bursting...
2015-05-14 22:31:42 -04:00
/*AUTOINST*/
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
// Outputs
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
.rx_clkin (rx_clkin),
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
.rx_access (rx_access),
.rx_burst (rx_burst),
.rx_packet (rx_packet[PW-1:0]),
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
// Inputs
Fixing RX reset (again!) -async assert -sync deassert
2015-10-07 20:37:49 -04:00
.erx_io_reset (erx_io_reset),
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
Fixing RX reset (again!) -async assert -sync deassert
2015-10-07 20:37:49 -04:00
.idelay_value (idelay_value[44:0]),
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
.load_taps (load_taps),
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rx_wr_wait (rx_wr_wait),
.rx_rd_wait (rx_rd_wait));
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
/**************************************************************/
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
/*ELINK CORE LOGIC */
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
/**************************************************************/
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
/*erx_core AUTO_TEMPLATE ( .rx_packet (rx_packet[PW-1:0]),
.rx_access (rx_access),
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
.erx_cfg_wait (erx_cfg_wait),
.rx_rd_wait (rx_rd_wait),
.rx_wr_wait (rx_wr_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
);
*/
Reorg cleanup -renamed disty for consistency (there is an arbiter there now) -adding missing ID to etx/erx -New org working!
2015-05-12 07:41:48 -04:00
defparam erx_core.ID=ID;
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
erx_core erx_core ( .clk (rx_lclk_div4),
Reset and clock cleanup -In the default mode we now have 7 input clocks to basic elink -This is too many, need to simplify, not reasonable! -But with all the knobs on the MMCM, performance will be great... -WIP on bursting...
2015-05-14 22:31:42 -04:00
.reset (erx_reset),
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
/*AUTOINST*/
Organization changes -dma with packet format -using the fifo_cdc block
2015-05-03 23:29:32 -04:00
// Outputs
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rx_rd_wait (rx_rd_wait), // Templated
.rx_wr_wait (rx_wr_wait), // Templated
Fixing RX reset (again!) -async assert -sync deassert
2015-10-07 20:37:49 -04:00
.idelay_value (idelay_value[44:0]),
RX reset/clocking cleanup - Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
2015-10-07 19:12:57 -04:00
.load_taps (load_taps),
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rxrd_access (rxrd_fifo_access), // Templated
.rxrd_packet (rxrd_fifo_packet[PW-1:0]), // Templated
.rxrr_access (rxrr_fifo_access), // Templated
.rxrr_packet (rxrr_fifo_packet[PW-1:0]), // Templated
.rxwr_access (rxwr_fifo_access), // Templated
.rxwr_packet (rxwr_fifo_packet[PW-1:0]), // Templated
.erx_cfg_wait (erx_cfg_wait), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
Organization changes -dma with packet format -using the fifo_cdc block
2015-05-03 23:29:32 -04:00
// Inputs
Integrating clock approach change -clocks moved outside elink -new packet interface format between protocol and io block
2015-05-13 23:29:18 -04:00
.rx_packet (rx_packet[PW-1:0]), // Templated
.rx_access (rx_access), // Templated
.rx_burst (rx_burst),
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rxrd_wait (rxrd_fifo_wait), // Templated
.rxrr_wait (rxrr_fifo_wait), // Templated
.rxwr_wait (rxwr_fifo_wait), // Templated
.erx_cfg_access (erx_cfg_access), // Templated
.erx_cfg_packet (erx_cfg_packet[PW-1:0])); // Templated
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
/************************************************************/
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
/*FIFOs */
/************************************************************/
erx_fifo erx_fifo (
/*AUTOINST*/
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
// Outputs
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.rxrd_fifo_wait (rxrd_fifo_wait),
.rxrr_fifo_wait (rxrr_fifo_wait),
.rxwr_fifo_wait (rxwr_fifo_wait),
// Inputs
Reset and clock cleanup -In the default mode we now have 7 input clocks to basic elink -This is too many, need to simplify, not reasonable! -But with all the knobs on the MMCM, performance will be great... -WIP on bursting...
2015-05-14 22:31:42 -04:00
.erx_reset (erx_reset),
.sys_reset (sys_reset),
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rx_lclk_div4 (rx_lclk_div4),
.sys_clk (sys_clk),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
Complete redesign of configuration register file -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
.rxrd_fifo_access(rxrd_fifo_access),
.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
.rxrr_fifo_access(rxrr_fifo_access),
.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
Completing elink hierarchy change -splits out clock domains -makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
.rxwr_fifo_access(rxwr_fifo_access),
.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]));
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
Refactoring and fixing bugs... -back and forth with emmu, memory is now inside (for good) -renamed clocks in etx to clarify -updated logic in protocol and disty -updated clock module ...one more review pass and we are ready for testing...
2015-03-25 19:25:12 -04:00
endmodule // erx
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
// Local Variables:
Reset and clock cleanup -In the default mode we now have 7 input clocks to basic elink -This is too many, need to simplify, not reasonable! -But with all the knobs on the MMCM, performance will be great... -WIP on bursting...
2015-05-14 22:31:42 -04:00
// verilog-library-directories:(".")
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
// End:
Major cleanup, refactoring, and feature completion -adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas
2015-04-11 00:04:18 -04:00
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX
2014-12-14 17:18:53 -05:00
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