oh/mio/hdl/mio_regmap.vh

`ifndef MIO_REGMAP_VH_
 `define MIO_REGMAP_VH_
//Registers addr[5:2]
 `define MIO_CONFIG   4'd0 // general config
 `define MIO_STATUS   4'd1 // status
 `define MIO_CLKDIV   4'd2 // clk divider config
 `define MIO_CLKPHASE 4'd3 // clk divider config
 `define MIO_ODELAY   4'd4 // output data delay element
 `define MIO_IDELAY   4'd5 // input data delay element
 `define MIO_ADDR0    4'd6 // destination address for amode
 `define MIO_ADDR1    4'd7 // destination address for amode

`endif //  `ifndef MIO_REGMAP_VH_
Adding register - These can be used to make the configuration of the mio datapath programmable - This is what I should have done for the elink. Always separate the control from the datapath!! 2016-03-20 22:35:43 -04:00			`ifndef MIO_REGMAP_VH_
			`define MIO_REGMAP_VH_
Preparing for safer clock setting changes 2016-04-11 12:04:30 -04:00			`//Registers addr[5:2]`
Adding register - These can be used to make the configuration of the mio datapath programmable - This is what I should have done for the elink. Always separate the control from the datapath!! 2016-03-20 22:35:43 -04:00			`define MIO_CONFIG 4'd0 // general config
			`define MIO_STATUS 4'd1 // status
			`define MIO_CLKDIV 4'd2 // clk divider config
			`define MIO_CLKPHASE 4'd3 // clk divider config
			`define MIO_ODELAY 4'd4 // output data delay element
			`define MIO_IDELAY 4'd5 // input data delay element
Removed mio autoincrement mode -Have this handled in a more capable DMA (no need to duplicate functionality) -Adding frame polarity signal 2016-03-23 08:29:41 -04:00			`define MIO_ADDR0 4'd6 // destination address for amode
			`define MIO_ADDR1 4'd7 // destination address for amode
Adding register - These can be used to make the configuration of the mio datapath programmable - This is what I should have done for the elink. Always separate the control from the datapath!! 2016-03-20 22:35:43 -04:00
			`endif // `ifndef MIO_REGMAP_VH_


Preparing for safer clock setting changes 2016-04-11 12:04:30 -04:00