oh/elink/dv/run.sh

#!/bin/bash

#Linting in Verilator
#verilator --lint-only -F elink.cmd -DTARGET_VERILATOR

#Compiling sim
iverilog -f elink.cmd

#Running sim
./a.out
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`#!/bin/bash`
Major cleanup, refactoring, and feature completion -adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas 2015-04-11 00:04:18 -04:00
			`#Linting in Verilator`
			`#verilator --lint-only -F elink.cmd -DTARGET_VERILATOR`

Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`#Compiling sim`
			`iverilog -f elink.cmd`

			`#Running sim`
			`./a.out`