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Complete redesign of erx io logic
-Building from primitives -Work in progress, not quite complete
This commit is contained in:
Andreas Olofsson
parent
9dcde59979
commit
0214df5804
@ -1,233 +1,244 @@
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module erx_io (/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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rx_lclk_div4, rx_frame_par, rx_data_par,
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rx_clk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
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// Inputs
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reset, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
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rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
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reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
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);
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parameter IOSTANDARD = "LVDS_25";
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parameter PW = 104;
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//###########
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//# reset
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//###########
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input reset; // Reset (from ecfg)
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//###########
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//# eLink pins
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//###########
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
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//#########################
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//# reset, clocks
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//#########################
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input reset; // reset
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input rx_lclk; // fast I/O clock
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input rx_lclk_div4; // slow clock
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output rx_clk_pll; // clock output for pll
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//##########################
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//# elink pins
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//##########################
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input rxi_lclk_p, rxi_lclk_n; // rx clock input
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input rxi_frame_p, rxi_frame_n; // rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; // rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
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//#############
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//# Fabric interface, 1/8 bit rate of eLink
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//#############
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output rx_lclk_div4; // Parallel clock output (slow)
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output [7:0] rx_frame_par;
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output [63:0] rx_data_par;
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input rx_wr_wait;
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input rx_rd_wait;
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//##########################
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//# erx logic interface
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//##########################
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output rx_access;
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output rx_burst;
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output [PW-1:0] rx_packet;
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input rx_wr_wait;
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input rx_rd_wait;
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//############
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//# WIRES
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//############
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wire [7:0] rx_data; // High-speed serial data
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wire rx_frame; // serial frame
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wire rx_lclk; // Single-ended clock
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wire rx_lclk_s; // Serial clock after BUFIO
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wire [7:0] rxi_data; // High-speed serial data
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wire rxi_frame; // serial frame
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wire access_wide;
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reg valid_packet;
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wire [15:0] data_in;
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//############
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//# REGS
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//############
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reg [7:0] data_even_reg;
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reg [7:0] data_odd_reg;
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reg rx_frame;
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reg rx_frame_old;
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reg [111:0] rx_sample;
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reg [6:0] rx_pointer; //7 cycles
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reg access;
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reg burst;
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reg [PW-1:0] rx_packet_lclk;
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reg rx_access;
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reg [PW-1:0] rx_packet;
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reg rx_burst;
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//################################
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//# Input Buffers Instantiation
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//################################
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IBUFDS
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#(.DIFF_TERM ("TRUE"),
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.IOSTANDARD (IOSTANDARD))
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ibufds_rxdata[7:0]
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ibuf_data[7:0]
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(.I (rxi_data_p[7:0]),
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.IB (rxi_data_n[7:0]),
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.O (rx_data[7:0]));
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.IB (rxi_data_n[7:0]),
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.O (rxi_data[7:0]));
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IBUFDS
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#(.DIFF_TERM ("TRUE"),
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.IOSTANDARD (IOSTANDARD))
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ibuf_frame
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(.I (rxi_frame_p),
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.IB (rxi_frame_n),
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.O (rxi_frame));
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IBUFDS
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#(.DIFF_TERM ("TRUE"),
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.IOSTANDARD (IOSTANDARD))
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ibufds_rx_frame
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(.I (rxi_frame_p),
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.IB (rxi_frame_n),
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.O (rx_frame));
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//#####################
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//# Clock Buffers
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//#####################
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IBUFGDS
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#(.DIFF_TERM ("TRUE"),
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.IOSTANDARD (IOSTANDARD))
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ibufds_rxlclk
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(.I (rxi_lclk_p),
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.IB (rxi_lclk_n),
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.O (rx_lclk));
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BUFIO bufio_rxlclk
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(.I (rx_lclk),
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.O (rx_lclk_s));
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ibuf_lclk
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(.I (rxi_lclk_p),
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.IB (rxi_lclk_n),
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.O (rx_clk_pll)
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);
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// BUFR generates the slow clock
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BUFR
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#(.SIM_DEVICE("7SERIES"),
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.BUFR_DIVIDE("4"))
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rx_lclk_div4_buf
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(.O (rx_lclk_div4),
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.CE(1'b1),
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.CLR(reset),//no reset
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.I (rx_lclk));
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//#####################
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//# FRAME EDGE DETECTOR
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//#####################
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always @ (posedge rx_lclk or posedge reset)
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if(reset)
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begin
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rx_frame <= 1'b0;
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rx_frame_old <= rx_frame;
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end
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else
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begin
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rx_frame <= rxi_frame;
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rx_frame_old <= rx_frame;
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end
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assign new_tran = rx_frame & ~rx_frame_old;
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//#####################
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//# DDR SAMPLERS
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//#####################
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//odd bytes
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always @ (posedge rx_lclk)
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data_even_reg[7:0] <= rxi_data[7:0];
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//odd bytes
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always @ (negedge rx_lclk)
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data_odd_reg[7:0] <= rxi_data[7:0];
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assign data_in[15:0] = {data_odd_reg[7:0],data_even_reg[7:0]};
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//#####################
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//#CREATE 112 BIT PACKET
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//#####################
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//write Pointer
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always @ (posedge rx_lclk)
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if (~rx_frame)
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rx_pointer[6:0]<=7'b0000001; //new frame
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else if (rx_pointer[6])
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rx_pointer[6:0]<=7'b0001000; //anticipate burst
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else if(rx_frame)
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rx_pointer[6:0]<={rx_pointer[5:0],1'b0};//middle of frame
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//convert to 112 bit packet
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always @ (posedge rx_lclk)
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if(rx_frame)
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begin
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if(rx_pointer[0])
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rx_sample[15:0] <= data_in[15:0];
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if(rx_pointer[1])
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rx_sample[31:16] <= data_in[15:0];
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if(rx_pointer[2])
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rx_sample[47:32] <= data_in[15:0];
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if(rx_pointer[3])
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rx_sample[63:48] <= data_in[15:0];
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if(rx_pointer[4])
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rx_sample[79:64] <= data_in[15:0];
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if(rx_pointer[5])
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rx_sample[95:80] <= data_in[15:0];
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if(rx_pointer[6])
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rx_sample[111:96] <= data_in[15:0];
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end
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/*
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case(rx_pointer[7:0])
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8'b0000001: rx_sample[15:0] <= data_in[15:0];
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8'b0000010: rx_sample[31:16] <= data_in[15:0];
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8'b0000100: rx_sample[47:32] <= data_in[15:0];
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8'b0001000: rx_sample[63:48] <= data_in[15:0];
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8'b0010000: rx_sample[79:64] <= data_in[15:0];
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8'b0100000: rx_sample[95:80] <= data_in[15:0];
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8'b1000000: rx_sample[111:96] <= data_in[15:0];
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default: rx_sample[111:0] <= 'b0;
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endcase // case (rx_pointer)
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*/
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//#####################
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//#DATA VALID SIGNAL
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//#####################
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always @ (posedge rx_lclk)
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begin
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access <= rx_pointer[6];
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valid_packet <= access;//data pipeline
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end
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//###################################
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//#SAMPLE AND HOLD DATA
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//###################################
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//(..and shuffle data for 104 bit packet)
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always @ (posedge rx_lclk)
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if(access)
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begin
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//access
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burst <= rx_frame; //burst detected (for next cycle)
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rx_packet_lclk[0] <= rx_sample[40];
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//write
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rx_packet_lclk[1] <= rx_sample[41];
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//datamode
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rx_packet_lclk[3:2] <= rx_sample[43:42];
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//ctrlmode
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rx_packet_lclk[7:4] <= rx_sample[15:12];
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//dstaddr
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rx_packet_lclk[39:8] <= {rx_sample[11:8],
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rx_sample[23:16],
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rx_sample[31:24],
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rx_sample[39:32],
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rx_sample[47:44]};
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//data
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rx_packet_lclk[71:40] <= {rx_sample[55:48],
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rx_sample[63:56],
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rx_sample[71:64],
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rx_sample[79:72]};
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//srcaddr
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rx_packet_lclk[103:72]<= {rx_sample[87:80],
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rx_sample[95:88],
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rx_sample[103:96],
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rx_sample[111:104]
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};
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end
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//###################################
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//#SYNCHRONIZE TO SLOW CLK
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//###################################
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//stretch access pulse to 4 cycles
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pulse_stretcher #(.DW(3)) ps0 (.out (access_wide),
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.in (valid_packet),
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.clk (rx_lclk),
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.reset (reset)
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);
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always @ (posedge rx_lclk_div4)
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rx_access <= access_wide;
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always @ (posedge rx_lclk_div4)
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if(access_wide)
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begin
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rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
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rx_burst <= burst;
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end
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//#############################
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//# Deserializer instantiations
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//#############################
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genvar i;
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generate for(i=0; i<8; i=i+1)
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begin : gen_serdes
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ISERDESE2
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#(
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.DATA_RATE("DDR"), // DDR, SDR
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.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
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.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
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.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
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// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
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.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
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.NUM_CE(2), // Number of clock enables (1,2)
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.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
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.SERDES_MODE("MASTER"), // MASTER, SLAVE
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// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_rxdata
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(
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.O(), // 1-bit output: Combinatorial output
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// Q1 - Q8: 1-bit (each) output: Registered data outputs
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.Q1(rx_data_par[i]), // Last data in?
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.Q2(rx_data_par[i+8]),
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.Q3(rx_data_par[i+16]),
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.Q4(rx_data_par[i+24]),
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.Q5(rx_data_par[i+32]),
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.Q6(rx_data_par[i+40]),
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.Q7(rx_data_par[i+48]),
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.Q8(rx_data_par[i+56]), // First data in?
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// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
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// synchronous to CLKDIV when asserted (active High). Subsequently, the data
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// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
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// operation, one position every time Bitslip is invoked. DDR operation is
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// different from SDR.
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(1'b0), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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.CLK(rx_lclk_s), // 1-bit input: High-speed clock
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.CLKB(~rx_lclk_s), // 1-bit input: High-speed secondary clock
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.CLKDIV(rx_lclk_div4), // 1-bit input: Divided clock
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.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
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// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
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.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
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.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
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// Input Data: 1-bit (each) input: ISERDESE2 data input ports
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.D(rx_data[i]), // 1-bit input: Data input
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.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
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.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
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.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
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.RST(reset), // 1-bit input: Active high asynchronous reset
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// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0)
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);
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end // block: gen_serdes
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endgenerate
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ISERDESE2
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#(
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.DATA_RATE("DDR"), // DDR, SDR
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.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
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.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
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.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
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// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
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.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
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.NUM_CE(2), // Number of clock enables (1,2)
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.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
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.SERDES_MODE("MASTER"), // MASTER, SLAVE
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// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_rx_frame
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(
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.O(), // 1-bit output: Combinatorial output
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// Q1 - Q8: 1-bit (each) output: Registered data outputs
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.Q1(rx_frame_par[0]),
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.Q2(rx_frame_par[1]),
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.Q3(rx_frame_par[2]),
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.Q4(rx_frame_par[3]),
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.Q5(rx_frame_par[4]),
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.Q6(rx_frame_par[5]),
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.Q7(rx_frame_par[6]),
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.Q8(rx_frame_par[7]),
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// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
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// synchronous to CLKDIV when asserted (active High). Subsequently, the data
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// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
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// operation, one position every time Bitslip is invoked. DDR operation is
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// different from SDR.
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(1'b0), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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||||
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
|
||||
.CLKB(~rx_lclk_s), // 1-bit input: High-speed secondary clock
|
||||
.CLKDIV(rx_lclk_div4), // 1-bit input: Divided clock
|
||||
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
|
||||
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
|
||||
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
|
||||
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
|
||||
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
|
||||
.D(rx_frame), // 1-bit input: Data input
|
||||
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
|
||||
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
|
||||
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
|
||||
.RST(reset), // 1-bit input: Active high asynchronous reset
|
||||
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
|
||||
.SHIFTIN1(1'b0),
|
||||
.SHIFTIN2(1'b0)
|
||||
);
|
||||
|
||||
//#############
|
||||
//#####################################
|
||||
//# Wait signals (asynchronous)
|
||||
//#############
|
||||
//#####################################
|
||||
|
||||
OBUFDS
|
||||
#(
|
||||
@ -250,29 +261,27 @@ module erx_io (/*AUTOARG*/
|
||||
.OB(rxo_rd_wait_n),
|
||||
.I(rx_rd_wait)
|
||||
);
|
||||
|
||||
|
||||
endmodule // erx_io
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
|
||||
// End:
|
||||
|
||||
/*
|
||||
File: e_rx_io.v
|
||||
Copyright (C) 2014 Adapteva, Inc.
|
||||
Contributed by Andreas Olofsson <fred@adapteva.com>
|
||||
|
||||
This file is part of the Parallella Project .
|
||||
|
||||
Copyright (C) 2014 Adapteva, Inc.
|
||||
Contributed by Fred Huettig <fred@adapteva.com>
|
||||
Contributed by Andreas Olofsson <fred@adapteva.com>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program (see the file COPYING). If not, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program (see the file COPYING). If not, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user