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Fixing bug on 64 bit register write

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This commit is contained in:
Andreas Olofsson 2015-04-28 00:46:40 -04:00
parent 67a05c9363
commit 02812c03a8
1 changed files with 6 additions and 8 deletions
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14
elink/hdl/ecfg_if.v
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@ -66,13 +66,11 @@ module ecfg_if (/*AUTOARG*/
wire [63:0] rxwr_data; wire [63:0] rxwr_data;
wire [AW-1:0] txwr_dstaddr; wire [AW-1:0] txwr_dstaddr;
wire [AW-1:0] txwr_srcaddr; wire [AW-1:0] rxwr_dstaddr;
wire [AW-1:0] txrd_dstaddr; wire [AW-1:0] txrd_dstaddr;
wire [AW-1:0] txrd_srcaddr; wire [AW-1:0] txrd_srcaddr;
wire [AW-1:0] rxwr_dstaddr;
wire [AW-1:0] rxwr_srcaddr;
wire mi_wr; wire mi_wr;
wire mi_rd; wire mi_rd;
@ -129,8 +127,8 @@ module ecfg_if (/*AUTOARG*/
txwr_dstaddr[19:0]; txwr_dstaddr[19:0];
//Data (prepare for it) //Data (prepare for it)
assign mi_din[63:0] = rx_wr ? {rxwr_srcaddr[31:0],rxwr_data[31:0]} : assign mi_din[63:0] = rx_wr ? rxwr_data[63:0] :
{txwr_srcaddr[31:0],txwr_data[31:0]}; txwr_data[63:0];
//Interface clock (gate?) //Interface clock (gate?)
assign mi_clk = sys_clk; assign mi_clk = sys_clk;