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TX clock and reset cleanup
- more modular - two bits cominng from sys_clk elink config domain - drives the tx and rx from top level elink - from software you would probably write 2'b11 to reset both at same time
This commit is contained in:
Andreas Olofsson
parent
0f24486a5f
commit
028bf19382
@ -2,16 +2,16 @@ module axi_elink(/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, e_chipid, e_resetb, e_cclk_p, e_cclk_n,
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mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr,
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m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock,
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m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid,
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m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready,
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m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
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m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
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m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
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s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
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s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
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txo_data_n, chipid, chip_resetb, cclk_p, cclk_n, mailbox_not_empty,
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mailbox_full, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
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m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
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m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb,
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m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
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m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
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m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid,
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m_axi_rready, s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp,
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s_axi_bvalid, s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp,
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s_axi_rvalid, s_axi_wready,
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// Inputs
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reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
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rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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@ -62,9 +62,9 @@ module axi_elink(/*AUTOARG*/
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/********************************/
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/*EPIPHANY INTERFACE (I/O PINS) */
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/********************************/
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output [11:0] e_chipid; //chip id strap pins for Epiphany
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output e_resetb; //chip reset for Epiphany (active low)
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output e_cclk_p,e_cclk_n; //high speed clock (up to 1GHz) to Epiphany
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output [11:0] chipid; //chip id strap pins for Epiphany
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output chip_resetb; //chip reset for Epiphany (active low)
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output cclk_p,cclk_n; //high speed clock (up to 1GHz) to Epiphany
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/*****************************/
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/*MAILBOX (interrupts) */
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@ -184,17 +184,12 @@ module axi_elink(/*AUTOARG*/
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/*#############################################*/
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/*AUTOINPUT*/
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire elink_en; // From elink of elink.v
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wire elink_reset; // From eclocks of eclocks.v
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wire rx_lclk; // From eclocks of eclocks.v
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wire rx_lclk_div4; // From eclocks of eclocks.v
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wire rx_lclk_pll; // From elink of elink.v
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wire rxrd_access; // From elink of elink.v
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wire [PW-1:0] rxrd_packet; // From elink of elink.v
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wire rxrd_wait; // From emaxi of emaxi.v
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@ -205,9 +200,6 @@ module axi_elink(/*AUTOARG*/
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wire [PW-1:0] rxwr_packet; // From elink of elink.v
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wire rxwr_wait; // From emaxi of emaxi.v
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wire timeout; // From elink of elink.v
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wire tx_lclk; // From eclocks of eclocks.v
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wire tx_lclk90; // From eclocks of eclocks.v
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wire tx_lclk_div4; // From eclocks of eclocks.v
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wire txrd_access; // From esaxi of esaxi.v
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wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v
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wire txrd_wait; // From elink of elink.v
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@ -227,11 +219,9 @@ module axi_elink(/*AUTOARG*/
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defparam elink.IOSTD_ELINK = IOSTD_ELINK;
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defparam elink.ETYPE = ETYPE;
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elink elink(.reset (elink_reset),
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.por_reset (reset), //por reset needed for elink_en
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elink elink(.sys_reset (reset), //por reset needed for elink_en
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/*AUTOINST*/
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// Outputs
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.rx_lclk_pll (rx_lclk_pll),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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@ -242,8 +232,10 @@ module axi_elink(/*AUTOARG*/
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.e_chipid (e_chipid[11:0]),
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.elink_en (elink_en),
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.chipid (chipid[11:0]),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.chip_resetb (chip_resetb),
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.mailbox_not_empty (mailbox_not_empty),
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.mailbox_full (mailbox_full),
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.timeout (timeout),
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@ -258,11 +250,6 @@ module axi_elink(/*AUTOARG*/
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.txrr_wait (txrr_wait),
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// Inputs
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.sys_clk (sys_clk),
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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@ -283,28 +270,7 @@ module axi_elink(/*AUTOARG*/
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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//########################################################
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//CLOCK AND RESET
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//########################################################
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eclocks eclocks (.rx_clkin (rx_lclk_pll),
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/*AUTOINST*/
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// Outputs
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.e_cclk_p (e_cclk_p),
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.e_cclk_n (e_cclk_n),
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.elink_reset (elink_reset),
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.e_resetb (e_resetb),
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// Inputs
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.reset (reset),
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.elink_en (elink_en),
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.sys_clk (sys_clk));
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//########################################################
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//AXI SLAVE
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//########################################################
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@ -8,16 +8,23 @@
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module ecfg_elink (/*AUTOARG*/
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// Outputs
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txwr_gated_access, elink_en, clk_config, e_chipid,
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txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,
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chipid,
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// Inputs
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txwr_access, txwr_packet, clk, reset
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clk, por_reset, txwr_access, txwr_packet
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);
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parameter RFAW = 6; // 32 registers for now
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parameter PW = 104; // 32 registers for now
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parameter ID = 12'h000;
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parameter DEFAULT_CHIPID = 12'h808;
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/******************************/
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/*Clock/reset */
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/******************************/
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input clk;
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input por_reset; // POR "hard reset"
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/******************************/
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/*REGISTER ACCESS */
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/******************************/
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@ -28,24 +35,19 @@ module ecfg_elink (/*AUTOARG*/
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/*FILTERED WRITE FOR TX FIFO */
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/******************************/
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output txwr_gated_access;
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/******************************/
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/*Clock/reset */
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/******************************/
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input clk;
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input reset; // POR "hard reset"
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/******************************/
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/*Outputs */
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/******************************/
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output elink_en; // elink master enable
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output [15:0] clk_config; // clock settings (for pll)
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output [11:0] e_chipid; // chip-id for Epiphany
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output etx_soft_reset; // tx soft reset (level)
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output erx_soft_reset; // rx soft reset (level)
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output [15:0] clk_config; // clock settings (for pll)
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output [11:0] chipid; // chip-id for Epiphany
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg ecfg_reset_reg;
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reg [1:0] ecfg_reset_reg;
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reg [15:0] ecfg_clk_reg;
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reg [11:0] ecfg_chipid_reg;
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reg [31:0] mi_dout;
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@ -94,26 +96,27 @@ module ecfg_elink (/*AUTOARG*/
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/*FILTER ACCESS */
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/*****************************/
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assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
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ecfg_clk_write |
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ecfg_chipid_write);
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ecfg_clk_write |
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ecfg_chipid_write);
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//###########################
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//# RESET REG (ASYNC)
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//###########################
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always @ (posedge clk or posedge reset)
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if(reset)
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ecfg_reset_reg <= 1'b0;
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always @ (posedge clk or posedge por_reset)
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if(por_reset)
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ecfg_reset_reg[1:0] <= 'b0;
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else if (ecfg_reset_write)
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ecfg_reset_reg <= mi_din[0];
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ecfg_reset_reg[1:0] <= mi_din[1:0];
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assign elink_en =~ecfg_reset_reg; //always on, TODO: fix!
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assign etx_soft_reset = ecfg_reset_reg[0];
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assign erx_soft_reset = ecfg_reset_reg[1];
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//###########################
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//# CCLK/LCLK (PLL)
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//###########################
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//TODO: implement!
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always @ (posedge clk)
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if(reset)
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always @ (posedge clk or posedge por_reset)
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if(por_reset)
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ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
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else if (ecfg_clk_write)
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ecfg_clk_reg[15:0] <= mi_din[15:0];
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@ -123,13 +126,13 @@ module ecfg_elink (/*AUTOARG*/
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//###########################
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//# CHIPID
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//###########################
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always @ (posedge clk)
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if(reset)
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always @ (posedge clk or posedge por_reset)
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if(por_reset)
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ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
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else if (ecfg_chipid_write)
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ecfg_chipid_reg[11:0] <= mi_din[11:0];
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assign e_chipid[11:0]=ecfg_chipid_reg[5:2];
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assign chipid[11:0]=ecfg_chipid_reg[5:2];
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endmodule // ecfg_elink
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@ -23,7 +23,7 @@ module ecfg_if (/*AUTOARG*/
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/*Clocks/reset */
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/********************************/
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input clk;
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input reset;
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input reset; //async reset
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/********************************/
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/*Incoming Packet */
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@ -137,7 +137,7 @@ module ecfg_if (/*AUTOARG*/
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//Access out packet
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assign access_forward = (mi_rx_en | mi_rd);
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always @ (posedge clk)
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always @ (posedge clk or posedge reset)
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if(reset)
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access_out <= 1'b0;
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else if(~wait_in)
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@ -1,14 +1,13 @@
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module elink(/*AUTOARG*/
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// Outputs
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rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
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txo_data_p, txo_data_n, e_chipid, elink_en, mailbox_not_empty,
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, chipid, cclk_p, cclk_n, chip_resetb, mailbox_not_empty,
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mailbox_full, timeout, rxwr_access, rxwr_packet, rxrd_access,
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rxrd_packet, rxrr_access, rxrr_packet, txwr_wait, txrd_wait,
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txrr_wait,
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// Inputs
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por_reset, reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
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rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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sys_reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
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txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
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@ -25,16 +24,9 @@ module elink(/*AUTOARG*/
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/****************************/
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/*CLOCK AND RESET */
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/****************************/
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input por_reset; // por reset for elink en
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input reset; // hardware reset
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input sys_reset; // reset for
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input sys_clk; // a single system clock for master/slave FIFOs
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input tx_lclk; // fast tx clock for IO
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input tx_lclk90; // fast 90deg shifted lclk
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input tx_lclk_div4; // slow tx clock for core logic
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input rx_lclk; // rx input clock tweaked by pll for IO
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input rx_lclk_div4; // slow clock for rx logic
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output rx_lclk_pll; // rx_lclk pass through input for pll
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/********************************/
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/*ELINK RECEIVER */
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/********************************/
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@ -56,9 +48,10 @@ module elink(/*AUTOARG*/
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/*************************************/
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/*EPIPHANY MISC INTERFACE (I/O PINS) */
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/*************************************/
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output [11:0] e_chipid; // chip id strap pins for epiphany
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output elink_en; // master enable (reset) for elink/epiphany
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output [11:0] chipid; // chip id strap pins for epiphany
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output cclk_p, cclk_n; //chip clock
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output chip_resetb; // From etx of etx.v
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/*****************************/
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/*MAILBOX INTERRUPTS */
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/*****************************/
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@ -66,10 +59,10 @@ module elink(/*AUTOARG*/
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output mailbox_full;
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/*****************************/
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/*READBACK TIMEOUT (TBD) */
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/* */
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/*****************************/
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output timeout;
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/*****************************/
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/*SYSTEM SIDE INTERFACE */
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/*****************************/
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@ -109,6 +102,7 @@ module elink(/*AUTOARG*/
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/*#############################################*/
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/*AUTOINPUT*/
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//wire
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wire erx_cfg_access; // To erx of erx.v
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@ -120,13 +114,11 @@ module elink(/*AUTOARG*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [15:0] clk_config; // From ecfg_elink of ecfg_elink.v
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wire erx_cfg_wait; // From erx of erx.v
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wire erx_reset; // From ereset of ereset.v
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wire erx_soft_reset; // From ecfg_elink of ecfg_elink.v
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wire etx_cfg_access; // From etx of etx.v
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wire [PW-1:0] etx_cfg_packet; // From etx of etx.v
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wire etx_reset; // From ereset of ereset.v
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wire sys_reset; // From ereset of ereset.v
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wire etx_soft_reset; // From ecfg_elink of ecfg_elink.v
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wire txwr_gated_access; // From ecfg_elink of ecfg_elink.v
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// End of automatics
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@ -137,40 +129,24 @@ module elink(/*AUTOARG*/
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defparam ecfg_elink.ID=ID;
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ecfg_elink ecfg_elink (.clk (sys_clk),
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.reset (por_reset),
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.por_reset (sys_reset),
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.clk_config (),
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/*AUTOINST*/
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// Outputs
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.txwr_gated_access (txwr_gated_access),
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.elink_en (elink_en),
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.clk_config (clk_config[15:0]),
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.e_chipid (e_chipid[11:0]),
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.etx_soft_reset (etx_soft_reset),
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.erx_soft_reset (erx_soft_reset),
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.chipid (chipid[11:0]),
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// Inputs
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]));
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/***********************************************************/
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/*RESET CIRCUITRY */
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/***********************************************************/
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//Synchronize with each clock domain
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ereset ereset (
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/*AUTOINST*/
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||||
// Outputs
|
||||
.etx_reset (etx_reset),
|
||||
.erx_reset (erx_reset),
|
||||
.sys_reset (sys_reset),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.sys_clk (sys_clk),
|
||||
.tx_lclk_div4 (tx_lclk_div4),
|
||||
.rx_lclk_div4 (rx_lclk_div4));
|
||||
|
||||
/***********************************************************/
|
||||
/*RECEIVER */
|
||||
/***********************************************************/
|
||||
/*erx AUTO_TEMPLATE (
|
||||
.mi_dout (mi_rx_dout[]),
|
||||
.reset (erx_reset),
|
||||
.soft_reset (erx_soft_reset),
|
||||
);
|
||||
*/
|
||||
|
||||
@ -181,7 +157,6 @@ module elink(/*AUTOARG*/
|
||||
erx erx(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.rx_lclk_pll (rx_lclk_pll),
|
||||
.rxo_wr_wait_p (rxo_wr_wait_p),
|
||||
.rxo_wr_wait_n (rxo_wr_wait_n),
|
||||
.rxo_rd_wait_p (rxo_rd_wait_p),
|
||||
@ -197,11 +172,9 @@ module elink(/*AUTOARG*/
|
||||
.mailbox_full (mailbox_full),
|
||||
.mailbox_not_empty (mailbox_not_empty),
|
||||
// Inputs
|
||||
.erx_reset (erx_reset),
|
||||
.soft_reset (erx_soft_reset), // Templated
|
||||
.sys_reset (sys_reset),
|
||||
.sys_clk (sys_clk),
|
||||
.rx_lclk (rx_lclk),
|
||||
.rx_lclk_div4 (rx_lclk_div4),
|
||||
.rxi_lclk_p (rxi_lclk_p),
|
||||
.rxi_lclk_n (rxi_lclk_n),
|
||||
.rxi_frame_p (rxi_frame_p),
|
||||
@ -221,8 +194,8 @@ module elink(/*AUTOARG*/
|
||||
.emwr_\(.*\) (esaxi_emwr_\1[]),
|
||||
.emrq_\(.*\) (esaxi_emrq_\1[]),
|
||||
.emrr_\(.*\) (emaxi_emrr_\1[]),
|
||||
.reset (etx_reset),
|
||||
|
||||
.soft_reset (etx_soft_reset),
|
||||
.txwr_access (txwr_gated_access),
|
||||
);
|
||||
*/
|
||||
|
||||
@ -230,7 +203,7 @@ module elink(/*AUTOARG*/
|
||||
defparam etx.IOSTD_ELINK = IOSTD_ELINK;
|
||||
defparam etx.ETYPE = ETYPE;
|
||||
|
||||
etx etx(.txwr_access (txwr_gated_access),
|
||||
etx etx(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.txo_lclk_p (txo_lclk_p),
|
||||
@ -239,24 +212,25 @@ module elink(/*AUTOARG*/
|
||||
.txo_frame_n (txo_frame_n),
|
||||
.txo_data_p (txo_data_p[7:0]),
|
||||
.txo_data_n (txo_data_n[7:0]),
|
||||
.cclk_p (cclk_p),
|
||||
.cclk_n (cclk_n),
|
||||
.chip_resetb (chip_resetb),
|
||||
.txrd_wait (txrd_wait),
|
||||
.txwr_wait (txwr_wait),
|
||||
.txrr_wait (txrr_wait),
|
||||
.etx_cfg_access (etx_cfg_access),
|
||||
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
|
||||
// Inputs
|
||||
.etx_reset (etx_reset),
|
||||
.sys_reset (sys_reset),
|
||||
.soft_reset (etx_soft_reset), // Templated
|
||||
.sys_clk (sys_clk),
|
||||
.tx_lclk (tx_lclk),
|
||||
.tx_lclk90 (tx_lclk90),
|
||||
.tx_lclk_div4 (tx_lclk_div4),
|
||||
.txi_wr_wait_p (txi_wr_wait_p),
|
||||
.txi_wr_wait_n (txi_wr_wait_n),
|
||||
.txi_rd_wait_p (txi_rd_wait_p),
|
||||
.txi_rd_wait_n (txi_rd_wait_n),
|
||||
.txrd_access (txrd_access),
|
||||
.txrd_packet (txrd_packet[PW-1:0]),
|
||||
.txwr_access (txwr_gated_access), // Templated
|
||||
.txwr_packet (txwr_packet[PW-1:0]),
|
||||
.txrr_access (txrr_access),
|
||||
.txrr_packet (txrr_packet[PW-1:0]),
|
||||
@ -274,11 +248,11 @@ module elink(/*AUTOARG*/
|
||||
.packet_out (erx_cfg_packet[PW-1:0]),
|
||||
// Inputs
|
||||
.clk_in (tx_lclk_div4),
|
||||
.reset_in (etx_reset),
|
||||
.reset_in (sys_reset), //Fix this??
|
||||
.access_in (etx_cfg_access),
|
||||
.packet_in (etx_cfg_packet[PW-1:0]),
|
||||
.clk_out (rx_lclk_div4),
|
||||
.reset_out (erx_reset),
|
||||
.reset_out (sys_reset),
|
||||
.wait_in (erx_cfg_wait)
|
||||
);
|
||||
|
||||
|
||||
@ -1,13 +1,12 @@
|
||||
module etx(/*AUTOARG*/
|
||||
// Outputs
|
||||
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
|
||||
txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access,
|
||||
etx_cfg_packet,
|
||||
txo_data_n, cclk_p, cclk_n, chip_resetb, txrd_wait, txwr_wait,
|
||||
txrr_wait, etx_cfg_access, etx_cfg_packet,
|
||||
// Inputs
|
||||
etx_reset, sys_reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
|
||||
txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
|
||||
txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access,
|
||||
txrr_packet, etx_cfg_wait
|
||||
sys_reset, soft_reset, sys_clk, txi_wr_wait_p, txi_wr_wait_n,
|
||||
txi_rd_wait_p, txi_rd_wait_n, txrd_access, txrd_packet,
|
||||
txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait
|
||||
);
|
||||
parameter AW = 32;
|
||||
parameter DW = 32;
|
||||
@ -16,15 +15,13 @@ module etx(/*AUTOARG*/
|
||||
parameter ID = 12'h000;
|
||||
parameter IOSTD_ELINK = "LVDS_25";
|
||||
parameter ETYPE = 1;
|
||||
|
||||
//Synched resets
|
||||
input etx_reset; // reset for core logic
|
||||
input sys_reset; // reset for fifos
|
||||
input soft_reset; // software controlled reset
|
||||
|
||||
//Clocks
|
||||
input sys_clk; // clock for fifos
|
||||
input tx_lclk; // fast clock for io
|
||||
input tx_lclk90; // 90 deg shifted lclk
|
||||
input tx_lclk_div4; // slow clock for core logic
|
||||
|
||||
//Transmit signals for IO
|
||||
output txo_lclk_p, txo_lclk_n; // tx clock output
|
||||
@ -32,7 +29,11 @@ module etx(/*AUTOARG*/
|
||||
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
|
||||
input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
|
||||
input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
|
||||
|
||||
|
||||
//Epiphany Chip Signals
|
||||
output cclk_p,cclk_n;
|
||||
output chip_resetb;
|
||||
|
||||
//Read Request Channel Input
|
||||
input txrd_access;
|
||||
input [PW-1:0] txrd_packet;
|
||||
@ -58,6 +59,12 @@ module etx(/*AUTOARG*/
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire etx_reset; // From etx_clocks of etx_clocks.v
|
||||
wire tx_lclk; // From etx_clocks of etx_clocks.v
|
||||
wire tx_lclk90; // From etx_clocks of etx_clocks.v
|
||||
wire tx_lclk_div4; // From etx_clocks of etx_clocks.v
|
||||
// End of automatics
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire tx_access; // From etx_core of etx_core.v
|
||||
wire tx_burst; // From etx_core of etx_core.v
|
||||
wire tx_io_wait; // From etx_io of etx_io.v
|
||||
@ -74,7 +81,26 @@ module etx(/*AUTOARG*/
|
||||
wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
|
||||
wire txwr_fifo_wait; // From etx_core of etx_core.v
|
||||
|
||||
/************************************************************/
|
||||
/*Clocks */
|
||||
/************************************************************/
|
||||
etx_clocks etx_clocks (
|
||||
.etx_io_reset (etx_io_reset),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.tx_lclk (tx_lclk),
|
||||
.tx_lclk90 (tx_lclk90),
|
||||
.tx_lclk_div4 (tx_lclk_div4),
|
||||
.cclk_p (cclk_p),
|
||||
.cclk_n (cclk_n),
|
||||
.etx_reset (etx_reset),
|
||||
.chip_resetb (chip_resetb),
|
||||
// Inputs
|
||||
.sys_reset (sys_reset),
|
||||
.soft_reset (soft_reset),
|
||||
.sys_clk (sys_clk));
|
||||
|
||||
|
||||
/************************************************************/
|
||||
/*FIFOs */
|
||||
/************************************************************/
|
||||
@ -157,7 +183,7 @@ module etx(/*AUTOARG*/
|
||||
/***********************************************************/
|
||||
|
||||
defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
|
||||
etx_io etx_io (.reset (etx_reset),
|
||||
etx_io etx_io (.reset (etx_io_reset),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.txo_lclk_p (txo_lclk_p),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user