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TX clock and reset cleanup

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- more modular
- two bits cominng from sys_clk elink config domain
- drives the tx and rx from top level elink
- from software you would probably write 2'b11 to reset both at same time
This commit is contained in:
Andreas Olofsson 2015-10-07 19:15:29 -04:00
parent 0f24486a5f
commit 028bf19382
5 changed files with 121 additions and 152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
elink/hdl/axi_elink.v
View File

@ -2,16 +2,16 @@ module axi_elink(/*AUTOARG*/
// Outputs // Outputs
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, e_chipid, e_resetb, e_cclk_p, e_cclk_n, txo_data_n, chipid, chip_resetb, cclk_p, cclk_n, mailbox_not_empty,
mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr, mailbox_full, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb,
m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid,
m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready, m_axi_rready, s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp,
s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata, s_axi_bvalid, s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp,
s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready, s_axi_rvalid, s_axi_wready,
// Inputs // Inputs
reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
@ -62,9 +62,9 @@ module axi_elink(/*AUTOARG*/
/********************************/ /********************************/
/*EPIPHANY INTERFACE (I/O PINS) */ /*EPIPHANY INTERFACE (I/O PINS) */
/********************************/ /********************************/
output [11:0] e_chipid; //chip id strap pins for Epiphany output [11:0] chipid; //chip id strap pins for Epiphany
output e_resetb; //chip reset for Epiphany (active low) output chip_resetb; //chip reset for Epiphany (active low)
output e_cclk_p,e_cclk_n; //high speed clock (up to 1GHz) to Epiphany output cclk_p,cclk_n; //high speed clock (up to 1GHz) to Epiphany
/*****************************/ /*****************************/
/*MAILBOX (interrupts) */ /*MAILBOX (interrupts) */
@ -184,17 +184,12 @@ module axi_elink(/*AUTOARG*/
/*#############################################*/ /*#############################################*/
/*AUTOINPUT*/ /*AUTOINPUT*/
// End of automatics // End of automatics
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink_en; // From elink of elink.v
wire elink_reset; // From eclocks of eclocks.v
wire rx_lclk; // From eclocks of eclocks.v
wire rx_lclk_div4; // From eclocks of eclocks.v
wire rx_lclk_pll; // From elink of elink.v
wire rxrd_access; // From elink of elink.v wire rxrd_access; // From elink of elink.v
wire [PW-1:0] rxrd_packet; // From elink of elink.v wire [PW-1:0] rxrd_packet; // From elink of elink.v
wire rxrd_wait; // From emaxi of emaxi.v wire rxrd_wait; // From emaxi of emaxi.v
@ -205,9 +200,6 @@ module axi_elink(/*AUTOARG*/
wire [PW-1:0] rxwr_packet; // From elink of elink.v wire [PW-1:0] rxwr_packet; // From elink of elink.v
wire rxwr_wait; // From emaxi of emaxi.v wire rxwr_wait; // From emaxi of emaxi.v
wire timeout; // From elink of elink.v wire timeout; // From elink of elink.v
wire tx_lclk; // From eclocks of eclocks.v
wire tx_lclk90; // From eclocks of eclocks.v
wire tx_lclk_div4; // From eclocks of eclocks.v
wire txrd_access; // From esaxi of esaxi.v wire txrd_access; // From esaxi of esaxi.v
wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v
wire txrd_wait; // From elink of elink.v wire txrd_wait; // From elink of elink.v
@ -227,11 +219,9 @@ module axi_elink(/*AUTOARG*/
defparam elink.IOSTD_ELINK = IOSTD_ELINK; defparam elink.IOSTD_ELINK = IOSTD_ELINK;
defparam elink.ETYPE = ETYPE; defparam elink.ETYPE = ETYPE;
elink elink(.reset (elink_reset), elink elink(.sys_reset (reset), //por reset needed for elink_en
.por_reset (reset), //por reset needed for elink_en
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p), .rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n), .rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p), .rxo_rd_wait_p (rxo_rd_wait_p),
@ -242,8 +232,10 @@ module axi_elink(/*AUTOARG*/
.txo_frame_n (txo_frame_n), .txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]), .txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]), .txo_data_n (txo_data_n[7:0]),
.e_chipid (e_chipid[11:0]), .chipid (chipid[11:0]),
.elink_en (elink_en), .cclk_p (cclk_p),
.cclk_n (cclk_n),
.chip_resetb (chip_resetb),
.mailbox_not_empty (mailbox_not_empty), .mailbox_not_empty (mailbox_not_empty),
.mailbox_full (mailbox_full), .mailbox_full (mailbox_full),
.timeout (timeout), .timeout (timeout),
@ -258,11 +250,6 @@ module axi_elink(/*AUTOARG*/
.txrr_wait (txrr_wait), .txrr_wait (txrr_wait),
// Inputs // Inputs
.sys_clk (sys_clk), .sys_clk (sys_clk),
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.rxi_lclk_p (rxi_lclk_p), .rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n), .rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p), .rxi_frame_p (rxi_frame_p),
@ -283,28 +270,7 @@ module axi_elink(/*AUTOARG*/
.txrr_access (txrr_access), .txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0])); .txrr_packet (txrr_packet[PW-1:0]));
//########################################################
//CLOCK AND RESET
//########################################################
eclocks eclocks (.rx_clkin (rx_lclk_pll),
/*AUTOINST*/
// Outputs
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.e_cclk_p (e_cclk_p),
.e_cclk_n (e_cclk_n),
.elink_reset (elink_reset),
.e_resetb (e_resetb),
// Inputs
.reset (reset),
.elink_en (elink_en),
.sys_clk (sys_clk));
//######################################################## //########################################################
//AXI SLAVE //AXI SLAVE
//######################################################## //########################################################

55
elink/hdl/ecfg_elink.v
View File

@ -8,16 +8,23 @@
module ecfg_elink (/*AUTOARG*/ module ecfg_elink (/*AUTOARG*/
// Outputs // Outputs
txwr_gated_access, elink_en, clk_config, e_chipid, txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,
chipid,
// Inputs // Inputs
txwr_access, txwr_packet, clk, reset clk, por_reset, txwr_access, txwr_packet
); );
parameter RFAW = 6; // 32 registers for now parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now parameter PW = 104; // 32 registers for now
parameter ID = 12'h000; parameter ID = 12'h000;
parameter DEFAULT_CHIPID = 12'h808; parameter DEFAULT_CHIPID = 12'h808;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input por_reset; // POR "hard reset"
/******************************/ /******************************/
/*REGISTER ACCESS */ /*REGISTER ACCESS */
/******************************/ /******************************/
@ -28,24 +35,19 @@ module ecfg_elink (/*AUTOARG*/
/*FILTERED WRITE FOR TX FIFO */ /*FILTERED WRITE FOR TX FIFO */
/******************************/ /******************************/
output txwr_gated_access; output txwr_gated_access;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input reset; // POR "hard reset"
/******************************/ /******************************/
/*Outputs */ /*Outputs */
/******************************/ /******************************/
output elink_en; // elink master enable output etx_soft_reset; // tx soft reset (level)
output [15:0] clk_config; // clock settings (for pll) output erx_soft_reset; // rx soft reset (level)
output [11:0] e_chipid; // chip-id for Epiphany output [15:0] clk_config; // clock settings (for pll)
output [11:0] chipid; // chip-id for Epiphany
/*------------------------CODE BODY---------------------------------------*/ /*------------------------CODE BODY---------------------------------------*/
//registers //registers
reg ecfg_reset_reg; reg [1:0] ecfg_reset_reg;
reg [15:0] ecfg_clk_reg; reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_chipid_reg; reg [11:0] ecfg_chipid_reg;
reg [31:0] mi_dout; reg [31:0] mi_dout;
@ -94,26 +96,27 @@ module ecfg_elink (/*AUTOARG*/
/*FILTER ACCESS */ /*FILTER ACCESS */
/*****************************/ /*****************************/
assign txwr_gated_access = txwr_access & ~(ecfg_reset_write | assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
ecfg_clk_write | ecfg_clk_write |
ecfg_chipid_write); ecfg_chipid_write);
//########################### //###########################
//# RESET REG (ASYNC) //# RESET REG (ASYNC)
//########################### //###########################
always @ (posedge clk or posedge reset) always @ (posedge clk or posedge por_reset)
if(reset) if(por_reset)
ecfg_reset_reg <= 1'b0; ecfg_reset_reg[1:0] <= 'b0;
else if (ecfg_reset_write) else if (ecfg_reset_write)
ecfg_reset_reg <= mi_din[0]; ecfg_reset_reg[1:0] <= mi_din[1:0];
assign elink_en =~ecfg_reset_reg; //always on, TODO: fix! assign etx_soft_reset = ecfg_reset_reg[0];
assign erx_soft_reset = ecfg_reset_reg[1];
//########################### //###########################
//# CCLK/LCLK (PLL) //# CCLK/LCLK (PLL)
//########################### //###########################
//TODO: implement! //TODO: implement!
always @ (posedge clk) always @ (posedge clk or posedge por_reset)
if(reset) if(por_reset)
ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
else if (ecfg_clk_write) else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0]; ecfg_clk_reg[15:0] <= mi_din[15:0];
@ -123,13 +126,13 @@ module ecfg_elink (/*AUTOARG*/
//########################### //###########################
//# CHIPID //# CHIPID
//########################### //###########################
always @ (posedge clk) always @ (posedge clk or posedge por_reset)
if(reset) if(por_reset)
ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID; ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
else if (ecfg_chipid_write) else if (ecfg_chipid_write)
ecfg_chipid_reg[11:0] <= mi_din[11:0]; ecfg_chipid_reg[11:0] <= mi_din[11:0];
assign e_chipid[11:0]=ecfg_chipid_reg[5:2]; assign chipid[11:0]=ecfg_chipid_reg[5:2];
endmodule // ecfg_elink endmodule // ecfg_elink

4
elink/hdl/ecfg_if.v
View File

@ -23,7 +23,7 @@ module ecfg_if (/*AUTOARG*/
/*Clocks/reset */ /*Clocks/reset */
/********************************/ /********************************/
input clk; input clk;
input reset; input reset; //async reset
/********************************/ /********************************/
/*Incoming Packet */ /*Incoming Packet */
@ -137,7 +137,7 @@ module ecfg_if (/*AUTOARG*/
//Access out packet //Access out packet
assign access_forward = (mi_rx_en | mi_rd); assign access_forward = (mi_rx_en | mi_rd);
always @ (posedge clk) always @ (posedge clk or posedge reset)
if(reset) if(reset)
access_out <= 1'b0; access_out <= 1'b0;
else if(~wait_in) else if(~wait_in)

90
elink/hdl/elink.v
View File

@ -1,14 +1,13 @@
module elink(/*AUTOARG*/ module elink(/*AUTOARG*/
// Outputs // Outputs
rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_p, txo_data_n, e_chipid, elink_en, mailbox_not_empty, txo_data_n, chipid, cclk_p, cclk_n, chip_resetb, mailbox_not_empty,
mailbox_full, timeout, rxwr_access, rxwr_packet, rxrd_access, mailbox_full, timeout, rxwr_access, rxwr_packet, rxrd_access,
rxrd_packet, rxrr_access, rxrr_packet, txwr_wait, txrd_wait, rxrd_packet, rxrr_access, rxrr_packet, txwr_wait, txrd_wait,
txrr_wait, txrr_wait,
// Inputs // Inputs
por_reset, reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, sys_reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n, rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait, txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access, txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
@ -25,16 +24,9 @@ module elink(/*AUTOARG*/
/****************************/ /****************************/
/*CLOCK AND RESET */ /*CLOCK AND RESET */
/****************************/ /****************************/
input por_reset; // por reset for elink en input sys_reset; // reset for
input reset; // hardware reset
input sys_clk; // a single system clock for master/slave FIFOs input sys_clk; // a single system clock for master/slave FIFOs
input tx_lclk; // fast tx clock for IO
input tx_lclk90; // fast 90deg shifted lclk
input tx_lclk_div4; // slow tx clock for core logic
input rx_lclk; // rx input clock tweaked by pll for IO
input rx_lclk_div4; // slow clock for rx logic
output rx_lclk_pll; // rx_lclk pass through input for pll
/********************************/ /********************************/
/*ELINK RECEIVER */ /*ELINK RECEIVER */
/********************************/ /********************************/
@ -56,9 +48,10 @@ module elink(/*AUTOARG*/
/*************************************/ /*************************************/
/*EPIPHANY MISC INTERFACE (I/O PINS) */ /*EPIPHANY MISC INTERFACE (I/O PINS) */
/*************************************/ /*************************************/
output [11:0] e_chipid; // chip id strap pins for epiphany output [11:0] chipid; // chip id strap pins for epiphany
output elink_en; // master enable (reset) for elink/epiphany output cclk_p, cclk_n; //chip clock
output chip_resetb; // From etx of etx.v
/*****************************/ /*****************************/
/*MAILBOX INTERRUPTS */ /*MAILBOX INTERRUPTS */
/*****************************/ /*****************************/
@ -66,10 +59,10 @@ module elink(/*AUTOARG*/
output mailbox_full; output mailbox_full;
/*****************************/ /*****************************/
/*READBACK TIMEOUT (TBD) */ /* */
/*****************************/ /*****************************/
output timeout; output timeout;
/*****************************/ /*****************************/
/*SYSTEM SIDE INTERFACE */ /*SYSTEM SIDE INTERFACE */
/*****************************/ /*****************************/
@ -109,6 +102,7 @@ module elink(/*AUTOARG*/
/*#############################################*/ /*#############################################*/
/*AUTOINPUT*/ /*AUTOINPUT*/
//wire //wire
wire erx_cfg_access; // To erx of erx.v wire erx_cfg_access; // To erx of erx.v
@ -120,13 +114,11 @@ module elink(/*AUTOARG*/
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] clk_config; // From ecfg_elink of ecfg_elink.v
wire erx_cfg_wait; // From erx of erx.v wire erx_cfg_wait; // From erx of erx.v
wire erx_reset; // From ereset of ereset.v wire erx_soft_reset; // From ecfg_elink of ecfg_elink.v
wire etx_cfg_access; // From etx of etx.v wire etx_cfg_access; // From etx of etx.v
wire [PW-1:0] etx_cfg_packet; // From etx of etx.v wire [PW-1:0] etx_cfg_packet; // From etx of etx.v
wire etx_reset; // From ereset of ereset.v wire etx_soft_reset; // From ecfg_elink of ecfg_elink.v
wire sys_reset; // From ereset of ereset.v
wire txwr_gated_access; // From ecfg_elink of ecfg_elink.v wire txwr_gated_access; // From ecfg_elink of ecfg_elink.v
// End of automatics // End of automatics
@ -137,40 +129,24 @@ module elink(/*AUTOARG*/
defparam ecfg_elink.ID=ID; defparam ecfg_elink.ID=ID;
ecfg_elink ecfg_elink (.clk (sys_clk), ecfg_elink ecfg_elink (.clk (sys_clk),
.reset (por_reset), .por_reset (sys_reset),
.clk_config (),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.txwr_gated_access (txwr_gated_access), .txwr_gated_access (txwr_gated_access),
.elink_en (elink_en), .etx_soft_reset (etx_soft_reset),
.clk_config (clk_config[15:0]), .erx_soft_reset (erx_soft_reset),
.e_chipid (e_chipid[11:0]), .chipid (chipid[11:0]),
// Inputs // Inputs
.txwr_access (txwr_access), .txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0])); .txwr_packet (txwr_packet[PW-1:0]));
/***********************************************************/
/*RESET CIRCUITRY */
/***********************************************************/
//Synchronize with each clock domain
ereset ereset (
/*AUTOINST*/
// Outputs
.etx_reset (etx_reset),
.erx_reset (erx_reset),
.sys_reset (sys_reset),
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk_div4 (rx_lclk_div4));
/***********************************************************/ /***********************************************************/
/*RECEIVER */ /*RECEIVER */
/***********************************************************/ /***********************************************************/
/*erx AUTO_TEMPLATE ( /*erx AUTO_TEMPLATE (
.mi_dout (mi_rx_dout[]), .mi_dout (mi_rx_dout[]),
.reset (erx_reset), .soft_reset (erx_soft_reset),
); );
*/ */
@ -181,7 +157,6 @@ module elink(/*AUTOARG*/
erx erx( erx erx(
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p), .rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n), .rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p), .rxo_rd_wait_p (rxo_rd_wait_p),
@ -197,11 +172,9 @@ module elink(/*AUTOARG*/
.mailbox_full (mailbox_full), .mailbox_full (mailbox_full),
.mailbox_not_empty (mailbox_not_empty), .mailbox_not_empty (mailbox_not_empty),
// Inputs // Inputs
.erx_reset (erx_reset), .soft_reset (erx_soft_reset), // Templated
.sys_reset (sys_reset), .sys_reset (sys_reset),
.sys_clk (sys_clk), .sys_clk (sys_clk),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.rxi_lclk_p (rxi_lclk_p), .rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n), .rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p), .rxi_frame_p (rxi_frame_p),
@ -221,8 +194,8 @@ module elink(/*AUTOARG*/
.emwr_\(.*\) (esaxi_emwr_\1[]), .emwr_\(.*\) (esaxi_emwr_\1[]),
.emrq_\(.*\) (esaxi_emrq_\1[]), .emrq_\(.*\) (esaxi_emrq_\1[]),
.emrr_\(.*\) (emaxi_emrr_\1[]), .emrr_\(.*\) (emaxi_emrr_\1[]),
.reset (etx_reset), .soft_reset (etx_soft_reset),
.txwr_access (txwr_gated_access),
); );
*/ */
@ -230,7 +203,7 @@ module elink(/*AUTOARG*/
defparam etx.IOSTD_ELINK = IOSTD_ELINK; defparam etx.IOSTD_ELINK = IOSTD_ELINK;
defparam etx.ETYPE = ETYPE; defparam etx.ETYPE = ETYPE;
etx etx(.txwr_access (txwr_gated_access), etx etx(
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.txo_lclk_p (txo_lclk_p), .txo_lclk_p (txo_lclk_p),
@ -239,24 +212,25 @@ module elink(/*AUTOARG*/
.txo_frame_n (txo_frame_n), .txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]), .txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]), .txo_data_n (txo_data_n[7:0]),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.chip_resetb (chip_resetb),
.txrd_wait (txrd_wait), .txrd_wait (txrd_wait),
.txwr_wait (txwr_wait), .txwr_wait (txwr_wait),
.txrr_wait (txrr_wait), .txrr_wait (txrr_wait),
.etx_cfg_access (etx_cfg_access), .etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), .etx_cfg_packet (etx_cfg_packet[PW-1:0]),
// Inputs // Inputs
.etx_reset (etx_reset),
.sys_reset (sys_reset), .sys_reset (sys_reset),
.soft_reset (etx_soft_reset), // Templated
.sys_clk (sys_clk), .sys_clk (sys_clk),
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.txi_wr_wait_p (txi_wr_wait_p), .txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n), .txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p), .txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n), .txi_rd_wait_n (txi_rd_wait_n),
.txrd_access (txrd_access), .txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]), .txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_gated_access), // Templated
.txwr_packet (txwr_packet[PW-1:0]), .txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access), .txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]), .txrr_packet (txrr_packet[PW-1:0]),
@ -274,11 +248,11 @@ module elink(/*AUTOARG*/
.packet_out (erx_cfg_packet[PW-1:0]), .packet_out (erx_cfg_packet[PW-1:0]),
// Inputs // Inputs
.clk_in (tx_lclk_div4), .clk_in (tx_lclk_div4),
.reset_in (etx_reset), .reset_in (sys_reset), //Fix this??
.access_in (etx_cfg_access), .access_in (etx_cfg_access),
.packet_in (etx_cfg_packet[PW-1:0]), .packet_in (etx_cfg_packet[PW-1:0]),
.clk_out (rx_lclk_div4), .clk_out (rx_lclk_div4),
.reset_out (erx_reset), .reset_out (sys_reset),
.wait_in (erx_cfg_wait) .wait_in (erx_cfg_wait)
); );

50
elink/hdl/etx.v
View File

@ -1,13 +1,12 @@
module etx(/*AUTOARG*/ module etx(/*AUTOARG*/
// Outputs // Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access, txo_data_n, cclk_p, cclk_n, chip_resetb, txrd_wait, txwr_wait,
etx_cfg_packet, txrr_wait, etx_cfg_access, etx_cfg_packet,
// Inputs // Inputs
etx_reset, sys_reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, sys_reset, soft_reset, sys_clk, txi_wr_wait_p, txi_wr_wait_n,
txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, txi_rd_wait_p, txi_rd_wait_n, txrd_access, txrd_packet,
txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access, txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait
txrr_packet, etx_cfg_wait
); );
parameter AW = 32; parameter AW = 32;
parameter DW = 32; parameter DW = 32;
@ -16,15 +15,13 @@ module etx(/*AUTOARG*/
parameter ID = 12'h000; parameter ID = 12'h000;
parameter IOSTD_ELINK = "LVDS_25"; parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1; parameter ETYPE = 1;
//Synched resets //Synched resets
input etx_reset; // reset for core logic
input sys_reset; // reset for fifos input sys_reset; // reset for fifos
input soft_reset; // software controlled reset
//Clocks //Clocks
input sys_clk; // clock for fifos input sys_clk; // clock for fifos
input tx_lclk; // fast clock for io
input tx_lclk90; // 90 deg shifted lclk
input tx_lclk_div4; // slow clock for core logic
//Transmit signals for IO //Transmit signals for IO
output txo_lclk_p, txo_lclk_n; // tx clock output output txo_lclk_p, txo_lclk_n; // tx clock output
@ -32,7 +29,11 @@ module etx(/*AUTOARG*/
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate) output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
//Epiphany Chip Signals
output cclk_p,cclk_n;
output chip_resetb;
//Read Request Channel Input //Read Request Channel Input
input txrd_access; input txrd_access;
input [PW-1:0] txrd_packet; input [PW-1:0] txrd_packet;
@ -58,6 +59,12 @@ module etx(/*AUTOARG*/
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire etx_reset; // From etx_clocks of etx_clocks.v
wire tx_lclk; // From etx_clocks of etx_clocks.v
wire tx_lclk90; // From etx_clocks of etx_clocks.v
wire tx_lclk_div4; // From etx_clocks of etx_clocks.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_access; // From etx_core of etx_core.v wire tx_access; // From etx_core of etx_core.v
wire tx_burst; // From etx_core of etx_core.v wire tx_burst; // From etx_core of etx_core.v
wire tx_io_wait; // From etx_io of etx_io.v wire tx_io_wait; // From etx_io of etx_io.v
@ -74,7 +81,26 @@ module etx(/*AUTOARG*/
wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txwr_fifo_wait; // From etx_core of etx_core.v wire txwr_fifo_wait; // From etx_core of etx_core.v
/************************************************************/
/*Clocks */
/************************************************************/
etx_clocks etx_clocks (
.etx_io_reset (etx_io_reset),
/*AUTOINST*/
// Outputs
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.etx_reset (etx_reset),
.chip_resetb (chip_resetb),
// Inputs
.sys_reset (sys_reset),
.soft_reset (soft_reset),
.sys_clk (sys_clk));
/************************************************************/ /************************************************************/
/*FIFOs */ /*FIFOs */
/************************************************************/ /************************************************************/
@ -157,7 +183,7 @@ module etx(/*AUTOARG*/
/***********************************************************/ /***********************************************************/
defparam etx_io.IOSTD_ELINK=IOSTD_ELINK; defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
etx_io etx_io (.reset (etx_reset), etx_io etx_io (.reset (etx_io_reset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.txo_lclk_p (txo_lclk_p), .txo_lclk_p (txo_lclk_p),