common/hdl: Fix syntax error when CFG_ASIC is undefined

Workaround for:
Recent Vivado (2016.4) synth step seems to have dropped support for
"-verilog_define CFG_ASIC=0"

Signed-off-by: Ola Jeppsson <ola@adapteva.com>

src/common/hdl/oh_buffer.v

@@ -11,6 +11,9 @@ module oh_buffer #(parameter N    = 1,  // number of inputs
      output [N-1:0] out // output
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;
 
    generate

src/common/hdl/oh_clockgate.v

@@ -12,6 +12,9 @@ module oh_clockgate (
      output eclk // enabled clock output
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
 
    generate

src/common/hdl/oh_clockmux.v

@@ -12,6 +12,9 @@ module oh_clockmux #(parameter N    = 1)    // number of clock inputs
     output 	  clkout 
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
     localparam ASIC = `CFG_ASIC;
 
     generate

src/common/hdl/oh_clockor.v

@@ -11,6 +11,9 @@ module oh_clockor #(parameter N    = 1)    // number of clock inputs
     output 	  clkout 
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;
 
    generate

src/common/hdl/oh_csa32.v

@@ -14,6 +14,9 @@ module oh_csa32 #(parameter DW   = 1 // data width
      output [DW-1:0] c   //carry
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use asic library
 
    generate

src/common/hdl/oh_csa42.v

@@ -17,6 +17,9 @@ module oh_csa42 #( parameter DW    = 1 // data width
      output [DW-1:0] cout  //carry out
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use asic library
 
    generate

src/common/hdl/oh_delay.v

@@ -13,6 +13,9 @@ module oh_delay  #(parameter DW   = 1, // width of data
     output [DW-1:0] out // output
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use asic library
    
    generate

src/common/hdl/oh_dsync.v

@@ -15,6 +15,9 @@ module oh_dsync  #(parameter PS    = 2,        // number of sync stages
     output dout    // synchronized data
     );
    
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use asic library
 
    generate

src/common/hdl/oh_lat0.v

@@ -12,6 +12,9 @@ module oh_lat0 #(parameter DW = 1            // data width
      output [DW-1:0] out  // output data (stable/latched when clk=1)
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
    
    generate

src/common/hdl/oh_lat1.v

@@ -12,6 +12,9 @@ module oh_lat1 #(parameter DW    = 1         //data width
      output [DW-1:0] out  // output data (stable/latched when clk=0)
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
 
    generate

src/common/hdl/oh_memory_dp.v

@@ -33,6 +33,9 @@ module oh_memory_dp # (parameter DW    = 104,      //memory width
     input [DW-1:0]  bist_din  // data input
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use asic library
    
    generate

src/common/hdl/oh_memory_sp.v

@@ -33,6 +33,9 @@ module oh_memory_sp  # (parameter DW    = 104,          // memory width
     input [DW-1:0]  bist_din  // data input
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
 
    generate

src/common/hdl/oh_pwr_gate.v

@@ -11,6 +11,9 @@ module oh_pwr_gate (
     output vddg     // gated output supply
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use asic library
 
 `ifdef TARGET_SIM

src/common/hdl/oh_pwr_isohi.v

@@ -13,6 +13,9 @@ module oh_pwr_isohi #(parameter DW   = 1        // width of data inputs
     output [DW-1:0] out // out = iso | in
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
 
    generate

src/common/hdl/oh_pwr_isolo.v

@@ -13,6 +13,9 @@ module oh_pwr_isolo #(parameter DW   = 1        // width of data inputs
     output [DW-1:0] out  // out = ~iso & in
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
    
    generate

src/common/hdl/oh_reg0.v

@@ -13,6 +13,9 @@ module ohr_reg0 #(parameter DW = 1            // data width
      output [DW-1:0] out  // output data (stable/latched when clk=1)
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
 
    generate

src/common/hdl/oh_reg1.v

@@ -13,6 +13,9 @@ module oh_reg1 #(parameter DW = 1            // data width
      output [DW-1:0] out  // output data (stable/latched when clk=1)
      );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;
    
    generate

src/common/hdl/oh_rsync.v

@@ -13,6 +13,9 @@ module oh_rsync #(parameter PS = 2          // number of sync stages
     output nrst_out
     );
 
+`ifndef CFG_ASIC
+ `define CFG_ASIC 0
+`endif
    localparam ASIC = `CFG_ASIC;  // use ASIC lib
 
    generate