Lint fixes for icarus/verilator

common/dv/libs.cmd

@@ -1,13 +1,7 @@
-#Always search local
 -y .
-
-#DV
 -y ../../common/dv
 -y ../../emesh/dv
 -y ../../memory/dv
-
-#HDL
--y .
 -y ../../common/hdl
 -y ../../elink/hdl
 -y ../../edma/hdl
@@ -17,11 +11,7 @@
 -y ../../memory/hdl
 -y ../../xilibs/hdl
 -y ../../parallella/hdl
-
-#FPGA
 -y ../../memory/fpga
-
-#INCLUDE PATHS (FOR CONSTANTS)
 +incdir+../../emesh/hdl
 +incdir+../../elink/hdl
 +incdir+../../edma/hdl

elink/dv/build.sh

@@ -8,7 +8,7 @@
 #
 dut="elink"
 top="../../common/dv/dv_top.v"
-iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp 
+iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp
 
 #PUT TARGET_SIM 
 

elink/dv/dut_elink.v

@@ -248,11 +248,11 @@ module dut(/*AUTOARG*/
                          );
   */
    //No read/write from elink1 (for now)
-   assign elink1_txrd_access = 1'b0;
-   assign elink1_txrd_packet = 'b0;
-   assign elink1_txwr_access = 1'b0;
-   assign elink1_txwr_packet = 'b0;
-   assign elink1_rxrr_wait   = 1'b0;
+   wire elink1_txrd_access = 1'b0;
+   wire elink1_txrd_packet = 'b0;
+   wire elink1_txwr_access = 1'b0;
+   wire elink1_txwr_packet = 'b0;
+   wire elink1_rxrr_wait   = 1'b0;
    
    defparam elink1.ID = 12'h820;   
    defparam elink1.ETYPE = 0; 
@@ -310,6 +310,8 @@ module dut(/*AUTOARG*/
 		 .rxrd_wait		(elink1_rxrd_wait));	 // Templated
    
 
+   wire emem_wait;
+   
    //"Arbitration" between read/write transaction   
    assign  emem_access           = elink1_rxwr_access | elink1_rxrd_access;      
 

elink/hdl/elink.v

@@ -157,7 +157,7 @@ module elink (/*AUTOARG*/
    defparam erx.ETYPE       = ETYPE;
    
    erx erx(.rx_active			(elink_active),
-	   .erx_nreset			(erx_nreset),
+	   .erx_nreset			(),
 	   /*AUTOINST*/
 	   // Outputs
 	   .rxo_wr_wait_p		(rxo_wr_wait_p),

elink/hdl/elink_cfg.v

@@ -61,7 +61,8 @@ module elink_cfg (/*AUTOARG*/
    wire 	mi_en;
    wire [31:0] 	mi_addr;
    wire [31:0] 	mi_din;
-
+   wire 	mi_we;
+   
    packet2emesh pe2 (
 		     // Outputs
 		     .write_out		(mi_we),

elink/hdl/erx_clocks.v

@@ -72,6 +72,7 @@ module erx_clocks (/*AUTOARG*/
    reg [2:0]   reset_state;
    wire        pll_reset;
    reg 	       rx_nreset;
+   wire        pll_locked;
    
    //Reset 
    assign rx_nreset_in  =  sys_nreset & tx_active;   

elink/hdl/erx_core.v

@@ -245,6 +245,7 @@ module erx_core (/*AUTOARG*/
 		      .packet_out	(ecfg_packet[PW-1:0]),	 // Templated
 		      // Inputs
 		      .clk		(clk),
+		      .nreset		(nreset),
 		      .access_in	(erx_cfg_access),	 // Templated
 		      .packet_in	(erx_cfg_packet[PW-1:0]), // Templated
 		      .mi_dout0		({32'b0,mi_cfg_dout[31:0]}), // Templated

elink/hdl/etx.v

@@ -63,6 +63,8 @@ module etx(/*AUTOARG*/
    wire			tx_lclk90;		// From etx_clocks of etx_clocks.v
    wire			tx_lclk_io;		// From etx_clocks of etx_clocks.v
    // End of automatics
+
+
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire			tx_access;		// From etx_core of etx_core.v
    wire			tx_burst;		// From etx_core of etx_core.v
@@ -78,12 +80,11 @@ module etx(/*AUTOARG*/
    wire			txwr_fifo_access;	// From etx_fifo of etx_fifo.v
    wire [PW-1:0]	txwr_fifo_packet;	// From etx_fifo of etx_fifo.v
    wire			txwr_fifo_wait;		// From etx_core of etx_core.v
-  
+   wire 		etx_io_nreset;
    /************************************************************/
    /*Clocks                                                    */
    /************************************************************/
-   etx_clocks etx_clocks (.etx_io_nreset	(etx_io_nreset),
-			  /*AUTOINST*/
+   etx_clocks etx_clocks (/*AUTOINST*/
 			  // Outputs
 			  .tx_lclk_io		(tx_lclk_io),
 			  .tx_lclk90		(tx_lclk90),
@@ -91,6 +92,7 @@ module etx(/*AUTOARG*/
 			  .cclk_p		(cclk_p),
 			  .cclk_n		(cclk_n),
 			  .etx_nreset		(etx_nreset),
+			  .etx_io_nreset	(etx_io_nreset),
 			  .chip_nreset		(chip_nreset),
 			  .tx_active		(tx_active),
 			  // Inputs
@@ -175,10 +177,14 @@ module etx(/*AUTOARG*/
    /***********************************************************/
    /*TRANSMIT I/O LOGIC                                       */
    /***********************************************************/
-
+   /*etx_io   AUTO_TEMPLATE (
+                           .nreset		(etx_io_nreset),
+    );
+    */
+   
    etx_io #(.ETYPE(ETYPE))
-   etx_io (.nreset		(etx_io_nreset),
-		  /*AUTOINST*/
+   etx_io (
+	   /*AUTOINST*/
 	   // Outputs
 	   .txo_lclk_p			(txo_lclk_p),
 	   .txo_lclk_n			(txo_lclk_n),
@@ -190,6 +196,7 @@ module etx(/*AUTOARG*/
 	   .tx_wr_wait			(tx_wr_wait),
 	   .tx_rd_wait			(tx_rd_wait),
 	   // Inputs
+	   .nreset			(etx_io_nreset),	 // Templated
 	   .tx_lclk_io			(tx_lclk_io),
 	   .tx_lclk90			(tx_lclk90),
 	   .txi_wr_wait_p		(txi_wr_wait_p),

elink/hdl/etx_cfg.v

@@ -67,7 +67,8 @@ module etx_cfg (/*AUTOARG*/
    wire 	   ecfg_tx_test_write;
    wire 	   ecfg_tx_addr_write;
    wire 	   ecfg_tx_data_write;
-   wire 	   loop_mode;
+   wire 	   ecfg_version_write;
+   wire 	   ecfg_tx_status_write;
    
    /*****************************/
    /*ADDRESS DECODE LOGIC       */

elink/hdl/etx_clocks.v

@@ -73,6 +73,10 @@ module etx_clocks (/*AUTOARG*/
    reg 	      mmcm_locked_sync;
    wire       lclk_locked;   
    wire       tx_nreset;
+   wire       mmcm_reset;
+   wire       tx_lclk;
+   wire       tx_lclk_div4_mmcm;
+   
    
    //###########################
    // RESET STATE MACHINE
@@ -155,7 +159,7 @@ module etx_clocks (/*AUTOARG*/
    rsync rsync_io (// Outputs
 		   .nrst_out		(etx_io_nreset),
 		   // Inputs
-		   .clk			(tx_lclk),
+		   .clk			(tx_lclk_io),
 		   .nrst_in		(tx_nreset));
    
    rsync rsync_core (// Outputs
@@ -215,7 +219,8 @@ module etx_clocks (/*AUTOARG*/
 	.PWRDWN(1'b0),
         .RST(mmcm_reset),     //reset
         .CLKFBIN(cclk_fb),
-        .CLKFBOUT(cclk_fb),  //feedback clock     
+        .CLKFBOUT(cclk_fb),  //feedback clock
+	.CLKFBOUTB(),        //inverted output feedback clock     
         .CLKIN1(sys_clk),    //input clock
 	.CLKIN2(1'b0),
 	.CLKINSEL(1'b1),      

elink/hdl/etx_core.v

@@ -136,6 +136,7 @@ module etx_core(/*AUTOARG*/
 		      .packet_out	(etx_cfg_packet[PW-1:0]), // Templated
 		      // Inputs
 		      .clk		(clk),
+		      .nreset		(nreset),
 		      .access_in	(etx_access),		 // Templated
 		      .packet_in	(etx_packet[PW-1:0]),	 // Templated
 		      .mi_dout0		({32'b0,mi_cfg_dout[31:0]}), // Templated

elink/hdl/etx_io.v

@@ -64,6 +64,8 @@ module etx_io (/*AUTOARG*/
    wire 	  txo_frame;   
    wire 	  txo_lclk90;
    reg 		  tx_io_ack;
+   wire 	  tx_new_frame;
+   wire 	  tx_lclk90_ddr;
    
    //#############################
    //# Transmit state machine

elink/hdl/etx_protocol.v

@@ -130,7 +130,7 @@ module etx_protocol (/*AUTOARG*/
 		     .srcaddr_out	(),
 		     .packet_in		(tx_packet[PW-1:0]));//input
 
-   assign burst_addr[31:0]  = (last_dstaddr[31:0] + 4'd8);
+   assign burst_addr[31:0]  = (last_dstaddr[31:0] + 32'h8);
    
    assign burst_addr_match  = (burst_addr[31:0] == etx_dstaddr[31:0]);
 

emailbox/hdl/emailbox.v

@@ -79,7 +79,7 @@ module emailbox (/*AUTOARG*/
    wire 	    mailbox_pop;
    wire [31:0] 	    emesh_addr;
    wire [63:0] 	    emesh_din;
-   wire 	    emesh__write;
+   wire 	    emesh_write;
    
    /*****************************/
    /*WRITE TO FIFO              */

emesh/dv/emesh_monitor.v

@@ -1,3 +1,4 @@
+/* verilator lint_off STMTDLY */
 module emesh_monitor(/*AUTOARG*/
    // Inputs
    clk, nreset, dut_access, dut_packet, wait_in, coreid
@@ -28,11 +29,9 @@ module emesh_monitor(/*AUTOARG*/
 	//TODO: Figure out these delays
 	#10
 	  //index should be core ID
-	    $sformat(tracefile,"%0s_%0h%s",NAME,coreid,".trace");
-	    ftrace  = $fopen({tracefile}, "w");  
+	  $sformat(tracefile,"%0s_%0h%s",NAME,coreid,".trace");
+	ftrace  = $fopen({tracefile}, "w");  
      end
-
-  
    
    always @ (posedge clk or negedge nreset)
      if(nreset & dut_access & ~wait_in)

xilibs/hdl/IDELAYE2.v

@@ -1,4 +1,5 @@
 `timescale 1ns/10ps
+/* verilator lint_off WIDTH */
 module IDELAYE2 (/*AUTOARG*/
    // Outputs
    CNTVALUEOUT, DATAOUT,

xilibs/hdl/MMCME2_ADV.v

@@ -1,3 +1,5 @@
+/* verilator lint_off STMTDLY */
+/* verilator lint_off WIDTH */
 `timescale 1ns/10ps
 module MMCME2_ADV # (
 		     parameter BANDWIDTH = "OPTIMIZED",

xilibs/hdl/PLLE2_ADV.v

@@ -1,5 +1,6 @@
 `timescale 1ns/10ps
-
+/* verilator lint_off STMTDLY */
+/* verilator lint_off WIDTH */
 module PLLE2_ADV #(
  
   parameter BANDWIDTH = "OPTIMIZED",
@@ -143,6 +144,7 @@ module PLLE2_ADV #(
    endgenerate
 
    reg [5:0] CLKOUT_DIV_LOCK;   
+
    always @ (posedge (CLKIN1 & vco_clk) or negedge (CLKIN1&~vco_clk))
      begin
 	CLKOUT_DIV_LOCK[5:0] <= CLKOUT_DIV[5:0];