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Improving standby circuit
- removing reset (bad logic) - refactor for simplicity/clarity - interface changes
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@ -5,43 +5,47 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_standby #( parameter PD = 5) //cycles to stay awake after "wakeup"
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module oh_standby #( parameter PD = 5, // cycles to stay awake after "wakeup"
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parameter N = 5) // event vector
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(
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input clkin, //clock input
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input nreset, //sync reset
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input wakeup, //wake up now!
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input idle, //core is in idle
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output clkout //clock output
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input clkin, //clock input
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input nreset,//async active low reset
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input [N-1:0] wakeup, //wake up event vector
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input idle, //core is in idle
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output clkout //clock output
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);
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//Wire declarations
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reg [PD-1:0] wakeup_pipe;
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reg idle_reg;
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wire state_change;
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wire clk_en;
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// detect an idle state change (wake up on any)
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always @ (posedge clkin)
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idle_reg <= idle;
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assign state_change = (idle ^ idle_reg);
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always @ (posedge clkin)
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wakeup_pipe[PD-1:0] <= {wakeup_pipe[PD-2:0],(state_change | wakeup)};
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wire clk_en;
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wire [N-1:0] wakeup_pulse;
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wire wakeup_now;
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//block enable signal
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assign clk_en = ~nreset | //always on during reset
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wakeup | //immediate wakeup
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state_change | //incoming transition
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// Wake up on any external event change
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oh_edge2pulse #(.DW(N))
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oh_edge2pulse (.out (wakeup_pulse[N-1:0]),
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.clk (clk),
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.nreset (nreset),
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.in (wakeup[N-1:0]));
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assign wakeup_now = |(wakeup_pulse[N-1:0]);
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// Stay away for PD cycles
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always @ (posedge clkin)
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wakeup_pipe[PD-1:0] <= {wakeup_pipe[PD-2:0], wakeup_now};
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// Clock enable
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assign clk_en = wakeup_now | //immediate wakeup
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(|wakeup_pipe[PD-1:0]) | //anything in pipe
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~idle; //core not in idle
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//clock gater (technology specific)
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// Clock gating cell
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oh_clockgate clockgate (.eclk(clkout),
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.clk(clkin),
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.en(clk_en),
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.nrst(nreset),
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.se(1'b0));
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.te(1'b0));
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endmodule // oh_standby
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