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Fixing MIO transmit DDR mode

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-iowidth refers to the size of a single ended bus
-DDR is implicitly half that size
This commit is contained in:
Andreas Olofsson 2016-08-25 21:01:01 -04:00
parent ebeeb1dd8b
commit 073d003e40
1 changed files with 5 additions and 4 deletions
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9
src/mio/hdl/mtx_io.v
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@ -39,7 +39,7 @@ module mtx_io #(parameter IOW = 64, // IO width
//# STATE MACHINE //# STATE MACHINE
//######################################## //########################################
assign dmode8 = (iowidth[1:0]==2'b00) & ~ddr_mode; assign dmode8 = (iowidth[1:0]==2'b00);
assign dmode16 = ((iowidth[1:0]==2'b01) & ~ddr_mode) | assign dmode16 = ((iowidth[1:0]==2'b01) & ~ddr_mode) |
(iowidth[1:0]==2'b00) & ddr_mode; (iowidth[1:0]==2'b00) & ddr_mode;
assign dmode32 = ((iowidth[1:0]==2'b10) & ~ddr_mode) | assign dmode32 = ((iowidth[1:0]==2'b10) & ~ddr_mode) |
@ -98,9 +98,10 @@ module mtx_io #(parameter IOW = 64, // IO width
// ddr circuit (one stage pipeline delay!) // ddr circuit (one stage pipeline delay!)
assign ddr_data_even[IOW/2-1:0] = shiftreg[IOW/2-1:0]; assign ddr_data_even[IOW/2-1:0] = shiftreg[IOW/2-1:0];
assign ddr_data_odd[IOW/2-1:0] = (iowidth[1:0]==2'b00) ? shiftreg[15:8] : assign ddr_data_odd[IOW/2-1:0] = (iowidth[1:0]==2'b00) ? shiftreg[7:4] : //byte
(iowidth[1:0]==2'b01) ? shiftreg[31:16] : (iowidth[1:0]==2'b01) ? shiftreg[15:8] : //short
shiftreg[63:32]; (iowidth[1:0]==2'b10) ? shiftreg[31:16] : //word
shiftreg[63:32]; //double
oh_oddr#(.DW(IOW/2)) oh_oddr#(.DW(IOW/2))
data_oddr (.out (tx_packet_ddr[IOW/2-1:0]), data_oddr (.out (tx_packet_ddr[IOW/2-1:0]),