FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity

MILESTONE: Open souce simulation elink loopback working!

Browse Source
This commit is contained in:
Andreas Olofsson 2015-04-17 15:51:55 -04:00
parent 7bc3b662ab
commit 08a31cd971
6 changed files with 271 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

170
elink/dv/dv_elink.v
View File

@ -1,15 +1,19 @@
module dv_elink(/*AUTOARG*/
// Outputs
dut_passed, dut_failed, dut_wr_wait, dut_rd_wait, dut_access,
dut_passed, dut_failed, dut_rd_wait, dut_wr_wait, dut_access,
dut_write, dut_datamode, dut_ctrlmode, dut_dstaddr, dut_srcaddr,
dut_data,
// Inputs
clk, reset, ext_access, ext_write, ext_datamode, ext_ctrlmode,
ext_dstaddr, ext_data, ext_srcaddr, ext_wr_wait, ext_rd_wait
ext_dstaddr, ext_data, ext_srcaddr, ext_rd_wait, ext_wr_wait
);
parameter AW=32;
parameter DW=32;
parameter CW=2; //number of clocks to send int
//Basic
input clk; // Core clock
input [CW-1:0] clk; // Core clock
input reset; // Reset
output dut_passed; // Indicates passing test
output dut_failed; // Indicates failing test
@ -22,8 +26,8 @@ module dv_elink(/*AUTOARG*/
input [31:0] ext_dstaddr;
input [31:0] ext_data;
input [31:0] ext_srcaddr;
output dut_rd_wait;
output dut_wr_wait;
output dut_rd_wait;
//Output Transaction
output dut_access;
@ -33,8 +37,8 @@ module dv_elink(/*AUTOARG*/
output [31:0] dut_dstaddr;
output [31:0] dut_srcaddr;
output [31:0] dut_data;
input ext_wr_wait;
input ext_rd_wait;
input ext_wr_wait;
/*AUTOINPUT*/
@ -132,6 +136,13 @@ module dv_elink(/*AUTOARG*/
wire [31:0] emaxi_emwr_dstaddr; // To emaxi of emaxi.v
wire [31:0] emaxi_emwr_srcaddr; // To emaxi of emaxi.v
wire emaxi_emwr_write; // To emaxi of emaxi.v
wire emaxi_emrr_access; // To emaxi of emaxi.v
wire [3:0] emaxi_emrr_ctrlmode; // To emaxi of emaxi.v
wire [31:0] emaxi_emrr_data; // To emaxi of emaxi.v
wire [1:0] emaxi_emrr_datamode; // To emaxi of emaxi.v
wire [31:0] emaxi_emrr_dstaddr; // To emaxi of emaxi.v
wire [31:0] emaxi_emrr_srcaddr; // To emaxi of emaxi.v
wire emaxi_emrr_write; // To emaxi of emaxi.v
wire esaxi_emrq_access; // From esaxi of esaxi.v
wire [3:0] esaxi_emrq_ctrlmode; // From esaxi of esaxi.v
@ -154,9 +165,20 @@ module dv_elink(/*AUTOARG*/
wire embox_not_empty;
wire cclk_p, cclk_n;
wire chip_resetb;
wire dut_access; // To dut_monitor of emesh_monitor.v
wire [3:0] dut_ctrlmode; // To dut_monitor of emesh_monitor.v
wire [DW-1:0] dut_data; // To dut_monitor of emesh_monitor.v
wire [1:0] dut_datamode; // To dut_monitor of emesh_monitor.v
wire [AW-1:0] dut_dstaddr; // To dut_monitor of emesh_monitor.v
wire [AW-1:0] dut_srcaddr; // To dut_monitor of emesh_monitor.v
wire dut_write; // To dut_monitor of emesh_monitor.v
//Clocks
wire clkin = clk[0];
wire m_axi_aclk = clk[1];
wire s_axi_aclk = clk[1];
//Splitting transaction into read/write path
//Read path
@ -178,13 +200,47 @@ module dv_elink(/*AUTOARG*/
assign emaxi_emwr_srcaddr[31:0] = ext_srcaddr[31:0];
//Master pushback
assign dut_rd_wait = ~emaxi_emrq_rd_en;
assign dut_wr_wait = ~emaxi_emwr_rd_en;
assign dut_rd_wait = ~emaxi_emrq_rd_en & emaxi_emrq_access;
assign dut_wr_wait = ~emaxi_emwr_rd_en & emaxi_emwr_access;
//Getting results back
//TODO: deal with collisions later
//btw, as I write this muxes...feeling that a datapacket is in order after all.
//maybe add a module for converting between packet and explicit signals....
assign dut_access = emaxi_emrr_access | esaxi_emwr_access | esaxi_emrq_access;
assign dut_write = emaxi_emrr_access ? emaxi_emrr_write :
esaxi_emwr_access ? esaxi_emwr_write :
esaxi_emrq_write;
assign dut_datamode[1:0] = emaxi_emrr_access ? emaxi_emrr_datamode[1:0] :
esaxi_emwr_access ? esaxi_emwr_datamode[1:0] :
esaxi_emrq_datamode[1:0];
assign dut_ctrlmode[3:0] = emaxi_emrr_access ? emaxi_emrr_ctrlmode[3:0] :
esaxi_emwr_access ? esaxi_emwr_ctrlmode[3:0] :
esaxi_emrq_ctrlmode[3:0];
assign dut_dstaddr[31:0] = emaxi_emrr_access ? emaxi_emrr_dstaddr[31:0] :
esaxi_emwr_access ? esaxi_emwr_dstaddr[31:0] :
esaxi_emrq_dstaddr[31:0];
assign dut_data[31:0] = emaxi_emrr_access ? emaxi_emrr_data[31:0] :
esaxi_emwr_access ? esaxi_emwr_data[31:0] :
esaxi_emrq_data[31:0];
assign dut_srcaddr[31:0] = emaxi_emrr_access ? emaxi_emrr_srcaddr[31:0] :
esaxi_emwr_access ? esaxi_emwr_srcaddr[31:0] :
esaxi_emrq_srcaddr[31:0];
/*emaxi AUTO_TEMPLATE (
// Outputs
.m_\(.*\) (dv_\1[]),
.emrr_\(.*\) (dut_\1[]),
.em\(.*\) (emaxi_em\1[]),
);
@ -193,18 +249,18 @@ module dv_elink(/*AUTOARG*/
//Drive the elink slave AXI interface
emaxi emaxi(.emrr_progfull (1'b0),
.m_axi_aresetn (~reset),
.m_axi_aclk (clk),
.m_axi_aclk (m_axi_aclk),
.emwr_rd_en (emaxi_emwr_rd_en),
.emrq_rd_en (emaxi_emrq_rd_en),
.emrr_access (emaxi_emrr_access),
.emrr_write (emaxi_emrr_write),
.emrr_datamode (emaxi_emrr_datamode[1:0]),
.emrr_ctrlmode (emaxi_emrr_ctrlmode[3:0]),
.emrr_dstaddr (emaxi_emrr_dstaddr[31:0]),
.emrr_data (emaxi_emrr_data[31:0]),
.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]),
/*AUTOINST*/
// Outputs
.emrr_access (dut_access), // Templated
.emrr_write (dut_write), // Templated
.emrr_datamode (dut_datamode[1:0]), // Templated
.emrr_ctrlmode (dut_ctrlmode[3:0]), // Templated
.emrr_dstaddr (dut_dstaddr[31:0]), // Templated
.emrr_data (dut_data[31:0]), // Templated
.emrr_srcaddr (dut_srcaddr[31:0]), // Templated
.m_axi_awaddr (dv_axi_awaddr[31:0]), // Templated
.m_axi_awlen (dv_axi_awlen[7:0]), // Templated
.m_axi_awsize (dv_axi_awsize[2:0]), // Templated
@ -274,7 +330,7 @@ module dv_elink(/*AUTOARG*/
.ecfg_coreid (12'h808),
.ecfg_timeout_enable (1'b0),
.s_axi_aresetn (~reset),
.s_axi_aclk (clk),
.s_axi_aclk (s_axi_aclk),
.emwr_access (esaxi_emwr_access),
.emwr_write (esaxi_emwr_write),
.emwr_datamode (esaxi_emwr_datamode[1:0]),
@ -354,12 +410,12 @@ module dv_elink(/*AUTOARG*/
.rowid (rowid[3:0]),
.s_axi_aresetn (~reset),
.m_axi_aresetn (~reset),
.s_axi_aclk (clk),
.m_axi_aclk (clk),
.s_axi_aclk (s_axi_aclk),
.m_axi_aclk (m_axi_aclk),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.clkin (clk),
.bypass_clocks ({clk,clk,clk}),
.clkin (clkin),
.bypass_clocks ({clkin,clkin,clkin}),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (wr_wait_p), // Templated
@ -446,7 +502,77 @@ module dv_elink(/*AUTOARG*/
.s_axi_wstrb (dv_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (dv_axi_wvalid)); // Templated
//Transaction Monitor
reg [31:0] etime;
always @ (posedge clkin or posedge reset)
if(reset)
etime[31:0] <= 32'b0;
else
etime[31:0] <= etime[31:0]+1'b1;
wire itrace = 1'b1;
/*emesh_monitor AUTO_TEMPLATE (
// Outputs
.txo_\(.*\) (\1[]),
.rxi_\(.*\) (\1[]),
.rxo_\(.*\) (\1[]),
.txi_\(.*\) (\1[]),
.s_\(.*\) (dv_\1[]),
.emesh_\(.*\) (@"(substring vl-cell-name 0 3)"_\1[]),
.m_axi_rdata ({32'b0,elink_axi_rdata[31:0]}), //restricted to slave width
);
*/
emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
/*AUTOINST*/
// Inputs
.clk (m_axi_aclk),
.reset (reset),
.itrace (itrace),
.etime (etime[31:0]),
.emesh_access (ext_access), // Templated
.emesh_write (ext_write), // Templated
.emesh_datamode (ext_datamode[1:0]), // Templated
.emesh_ctrlmode (ext_ctrlmode[3:0]), // Templated
.emesh_dstaddr (ext_dstaddr[AW-1:0]), // Templated
.emesh_data (ext_data[DW-1:0]), // Templated
.emesh_srcaddr (ext_srcaddr[AW-1:0])); // Templated
emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
/*AUTOINST*/
// Inputs
.clk (s_axi_aclk),
.reset (reset),
.itrace (itrace),
.etime (etime[31:0]),
.emesh_access (dut_access), // Templated
.emesh_write (dut_write), // Templated
.emesh_datamode (dut_datamode[1:0]), // Templated
.emesh_ctrlmode (dut_ctrlmode[3:0]), // Templated
.emesh_dstaddr (dut_dstaddr[AW-1:0]), // Templated
.emesh_data (dut_data[DW-1:0]), // Templated
.emesh_srcaddr (dut_srcaddr[AW-1:0])); // Templated
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

80
elink/dv/dv_elink_tb.v
View File

@ -1,9 +1,11 @@
module dv_elink_tb();
parameter AW=32;
parameter DW=32;
parameter CW=2; //number of clocks to send int
/* verilator lint_off STMTDLY */
/* verilator lint_off UNOPTFLAT */
//REGS
reg clk;
reg [1:0] clk;
reg reset;
reg go;
reg [1:0] datamode;
@ -17,10 +19,17 @@ module dv_elink_tb();
reg ext_wr_wait;
reg ext_rd_wait;
reg init;
//Forever clock
always
#10 clk = ~clk;
#10 clk[0] = ~clk[0];//clock for elink
always
#100 clk[1] = ~clk[1];//clock for axi interface
//should make variable to really test all fifos
wire clkstim = clk[1];
//Reset
initial
@ -28,8 +37,8 @@ module dv_elink_tb();
#0
reset = 1'b1; // reset is active
go = 1'b0;
clk = 1'b0;
datamode = 2'b11;
clk[1:0] = 2'b0;
datamode = 2'b10;
#400
//clock config (fast /2)
dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0113;
@ -40,13 +49,13 @@ module dv_elink_tb();
reset = 1'b0; // at time 100 release reset
#1000
go = 1'b1;
go = 1'b1;
#2000
datamode = 2'b10;
#3000
datamode = 2'b01;
#4000
#3000
datamode = 2'b00;
#4000
go = 1'b0;
#10000
$finish;
end
@ -55,28 +64,27 @@ module dv_elink_tb();
//To make this work, we limit the addresses to 64 bit aligned
always @ (posedge clk)
if(reset)
always @ (posedge clkstim)
if(reset | ~go)
begin
ext_access <=1'b0; //empty
ext_write <=1'b1;
ext_datamode[1:0] <=2'b0;
ext_ctrlmode[3:0] <=4'b0;
ext_data[31:0] <=32'b0;
ext_dstaddr[31:0] <=32'b0;
ext_srcaddr[31:0] <=32'b0;
ext_rd_wait <=1'b0;
ext_wr_wait <=1'b0;
ext_access <= 1'b0; //empty
ext_write <= 1'b1;
ext_datamode[1:0] <= 2'b0;
ext_ctrlmode[3:0] <= 4'b0;
ext_data[31:0] <= 32'b0;
ext_dstaddr[31:0] <= 32'b0;
ext_srcaddr[31:0] <= 32'b0;
ext_rd_wait <= 1'b0;
ext_wr_wait <= 1'b0;
end
else if ((go & ~ext_access) | (ext_access & ~dut_wr_wait))
else if (go & ~dut_wr_wait)
//else if ((go & ~ext_access) | (go & ext_access & ~dut_wr_wait))
begin
ext_access <= 1'b1;
ext_data[31:0] <= ext_data[31:0] + 32'b1;
ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
ext_srcaddr[31:0] <= ext_srcaddr[31:0] + 32'd8;//(32'b1<<datamode)
ext_datamode[1:0] <= datamode[1:0];
end
end
//Waveform dump
`ifndef TARGET_VERILATOR
initial
@ -106,8 +114,8 @@ always @ (posedge clk)
// Outputs
.dut_passed (dut_passed),
.dut_failed (dut_failed),
.dut_wr_wait (dut_wr_wait),
.dut_rd_wait (dut_rd_wait),
.dut_wr_wait (dut_wr_wait),
.dut_access (dut_access),
.dut_write (dut_write),
.dut_datamode (dut_datamode[1:0]),
@ -116,7 +124,7 @@ always @ (posedge clk)
.dut_srcaddr (dut_srcaddr[31:0]),
.dut_data (dut_data[31:0]),
// Inputs
.clk (clk),
.clk (clk[CW-1:0]),
.reset (reset),
.ext_access (ext_access),
.ext_write (ext_write),
@ -125,9 +133,23 @@ always @ (posedge clk)
.ext_dstaddr (ext_dstaddr[31:0]),
.ext_data (ext_data[31:0]),
.ext_srcaddr (ext_srcaddr[31:0]),
.ext_wr_wait (ext_wr_wait),
.ext_rd_wait (ext_rd_wait));
.ext_rd_wait (ext_rd_wait),
.ext_wr_wait (ext_wr_wait));
endmodule // dv_elink_tb
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

61
elink/dv/emesh_monitor.v Normal file
View File

@ -0,0 +1,61 @@
/* verilator lint_off WIDTH */
module emesh_monitor(/*AUTOARG*/
// Inputs
clk, reset, itrace, etime, emesh_access, emesh_write,
emesh_datamode, emesh_ctrlmode, emesh_dstaddr, emesh_data,
emesh_srcaddr, emesh_wait
);
parameter AW = 32;
parameter DW = 32;
parameter NAME = "cpu";
//BASIC INTERFACE
input clk;
input reset;
input itrace;
input [31:0] etime;
//MESH TRANSCTION
input emesh_access;
input emesh_write;
input [1:0] emesh_datamode;
input [3:0] emesh_ctrlmode;
input [AW-1:0] emesh_dstaddr;
input [DW-1:0] emesh_data;
input [AW-1:0] emesh_srcaddr;
input emesh_wait;
//core name for trace
reg [63:0] name=NAME;
reg [31:0] ftrace;
initial
begin
ftrace = $fopen({NAME,".trace"}, "w");
end
always @ (posedge clk)
if(itrace & ~reset & emesh_access & ~emesh_wait)
begin
//$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
$fwrite(ftrace, "%h_%h_%h_%h_%h\n",emesh_srcaddr[AW-1:0], emesh_data[DW-1:0],emesh_dstaddr[DW-1:0],emesh_ctrlmode[3:0],{emesh_datamode[1:0],emesh_write,emesh_access});
end
endmodule // emesh_monitor
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

23
elink/hdl/erx.v
View File

@ -17,7 +17,6 @@ module erx (/*AUTOARG*/
parameter DW = 32;
parameter RFAW = 13;
parameter MW = 44; //width of MMU lookup table
//Clocks and reset
input reset;
@ -94,13 +93,10 @@ module erx (/*AUTOARG*/
wire [63:0] emmu_dstaddr; // From emmu of emmu.v
wire [AW-1:0] emmu_srcaddr; // From emmu of emmu.v
wire emmu_write; // From emmu of emmu.v
wire emrq_full; // From m_rq_fifo of fifo_async_emesh.v
wire emrq_progfull; // From m_rq_fifo of fifo_async_emesh.v
wire emrq_wr_en; // From erx_disty of erx_disty.v
wire emrr_full; // From s_rr_fifo of fifo_async_emesh.v
wire emrr_progfull; // From s_rr_fifo of fifo_async_emesh.v
wire emrr_wr_en; // From erx_disty of erx_disty.v
wire emwr_full; // From m_wr_fifo of fifo_async_emesh.v
wire emwr_progfull; // From m_wr_fifo of fifo_async_emesh.v
wire emwr_wr_en; // From erx_disty of erx_disty.v
wire [3:0] erx_ctrlmode; // From erx_disty of erx_disty.v
@ -118,7 +114,10 @@ module erx (/*AUTOARG*/
//regs
reg [15:0] ecfg_rx_debug;
wire emrq_full;
wire emwr_full;
wire emrr_full;
/************************************************************/
/*FIFOs */
/*(for AXI 1. read request, 2. write, and 3. read response) */
@ -139,7 +138,8 @@ module erx (/*AUTOARG*/
*/
//Read request fifo (from Epiphany)
fifo_async_emesh m_rq_fifo(/*AUTOINST*/
fifo_async_emesh m_rq_fifo(.fifo_full (emrq_full),
/*AUTOINST*/
// Outputs
.emesh_access_out (emrq_access), // Templated
.emesh_write_out (emrq_write), // Templated
@ -148,7 +148,6 @@ module erx (/*AUTOARG*/
.emesh_dstaddr_out(emrq_dstaddr[31:0]), // Templated
.emesh_data_out (emrq_data[31:0]), // Templated
.emesh_srcaddr_out(emrq_srcaddr[31:0]), // Templated
.fifo_full (emrq_full), // Templated
.fifo_progfull (emrq_progfull), // Templated
// Inputs
.rd_clk (m_axi_aclk), // Templated
@ -164,7 +163,8 @@ module erx (/*AUTOARG*/
.fifo_read (emrq_rd_en)); // Templated
//Write fifo (from Epiphany)
fifo_async_emesh m_wr_fifo(/*AUTOINST*/
fifo_async_emesh m_wr_fifo(.fifo_full (emwr_full),
/*AUTOINST*/
// Outputs
.emesh_access_out (emwr_access), // Templated
.emesh_write_out (emwr_write), // Templated
@ -173,7 +173,6 @@ module erx (/*AUTOARG*/
.emesh_dstaddr_out(emwr_dstaddr[31:0]), // Templated
.emesh_data_out (emwr_data[31:0]), // Templated
.emesh_srcaddr_out(emwr_srcaddr[31:0]), // Templated
.fifo_full (emwr_full), // Templated
.fifo_progfull (emwr_progfull), // Templated
// Inputs
.rd_clk (m_axi_aclk), // Templated
@ -191,7 +190,7 @@ module erx (/*AUTOARG*/
//Read response fifo (for host)
fifo_async_emesh s_rr_fifo(
fifo_async_emesh s_rr_fifo(.fifo_full (emrr_full),
.emesh_access_out (),
.emesh_write_out (),
.emesh_datamode_out(),
@ -201,7 +200,6 @@ module erx (/*AUTOARG*/
/*AUTOINST*/
// Outputs
.emesh_data_out (emrr_data[31:0]), // Templated
.fifo_full (emrr_full), // Templated
.fifo_progfull (emrr_progfull), // Templated
// Inputs
.rd_clk (s_axi_aclk), // Templated
@ -254,11 +252,8 @@ module erx (/*AUTOARG*/
.emmu_dstaddr (emmu_dstaddr[31:0]),
.emmu_srcaddr (emmu_srcaddr[31:0]),
.emmu_data (emmu_data[31:0]),
.emwr_full (emwr_full),
.emwr_progfull (emwr_progfull),
.emrq_full (emrq_full),
.emrq_progfull (emrq_progfull),
.emrr_full (emrr_full),
.emrr_progfull (emrr_progfull),
.ecfg_rx_enable (ecfg_rx_enable));

13
elink/hdl/erx_disty.v
View File

@ -15,8 +15,8 @@ module erx_disty (/*AUTOARG*/
erx_data,
// Inputs
clk, mmu_en, emmu_access, emmu_write, emmu_datamode, emmu_ctrlmode,
emmu_dstaddr, emmu_srcaddr, emmu_data, emwr_full, emwr_progfull,
emrq_full, emrq_progfull, emrr_full, emrr_progfull, ecfg_rx_enable
emmu_dstaddr, emmu_srcaddr, emmu_data, emwr_progfull,
emrq_progfull, emrr_progfull, ecfg_rx_enable
);
parameter [11:0] C_READ_TAG_ADDR = 12'h810;
@ -42,17 +42,14 @@ module erx_disty (/*AUTOARG*/
// Master FIFO port, writes
output emwr_wr_en;
input emwr_full; // full flags for debug only
input emwr_progfull;
// Master FIFO port, read requests
output emrq_wr_en;
input emrq_full;
input emrq_progfull;
// Master FIFO port, read responses
output emrr_wr_en;
input emrr_full;
input emrr_progfull;
//Master Transaction for all FIFOs
@ -81,12 +78,6 @@ module erx_disty (/*AUTOARG*/
reg emrq_wr_en;
reg emrr_wr_en;
reg [1:0] rxmmu_sync;
//############
//# WIRES
//############
wire rxmmu = rxmmu_sync[0];
//############
//# PIPELINE AND DISTRIBUTE

1
elink/hdl/erx_io.v
View File

@ -324,7 +324,6 @@ reg [8:0] ecfg_rx_datain;
endmodule // erx_io
/*
File: e_rx_io.v