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Adding e16 elink golden reference to dv environment
This commit is contained in:
Andreas Olofsson
parent
0ca303432b
commit
08b871941d
@ -1,3 +1,9 @@
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`define CFG_FAKECLK 1 /*stupid verilator doesn't get clock gating*/
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`define CFG_MDW 32 /*Width of mesh network*/
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`define CFG_DW 32 /*Width of datapath*/
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`define CFG_AW 32 /*Width of address space*/
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`define CFG_LW 8 /*Link port width*/
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module dv_elink(/*AUTOARG*/
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// Outputs
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dut_passed, dut_failed, dut_rd_wait, dut_wr_wait, dut_access,
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@ -37,10 +43,10 @@ module dv_elink(/*AUTOARG*/
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wire elink0_cclk_n; // From elink0 of elink.v
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wire elink0_cclk_p; // From elink0 of elink.v
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wire elink0_chip_resetb; // From elink0 of elink.v
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wire [3:0] elink0_colid; // From elink0 of elink.v
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wire [11:0] elink0_chipid; // From elink0 of elink.v
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wire elink0_mailbox_full; // From elink0 of elink.v
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wire elink0_mailbox_not_empty;// From elink0 of elink.v
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wire [3:0] elink0_rowid; // From elink0 of elink.v
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wire elink0_rx_lclk_div4; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
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@ -52,6 +58,7 @@ module dv_elink(/*AUTOARG*/
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wire elink0_rxwr_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxwr_packet; // From elink0 of elink.v
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wire elink0_timeout; // From elink0 of elink.v
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wire elink0_tx_lclk_div4; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_n; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_p; // From elink0 of elink.v
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wire elink0_txo_frame_n; // From elink0 of elink.v
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@ -64,10 +71,10 @@ module dv_elink(/*AUTOARG*/
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wire elink1_cclk_n; // From elink1 of elink.v
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wire elink1_cclk_p; // From elink1 of elink.v
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wire elink1_chip_resetb; // From elink1 of elink.v
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wire [3:0] elink1_colid; // From elink1 of elink.v
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wire [11:0] elink1_chipid; // From elink1 of elink.v
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wire elink1_mailbox_full; // From elink1 of elink.v
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wire elink1_mailbox_not_empty;// From elink1 of elink.v
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wire [3:0] elink1_rowid; // From elink1 of elink.v
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wire elink1_rx_lclk_div4; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
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@ -79,6 +86,7 @@ module dv_elink(/*AUTOARG*/
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wire elink1_rxwr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
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wire elink1_timeout; // From elink1 of elink.v
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wire elink1_tx_lclk_div4; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_n; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_p; // From elink1 of elink.v
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wire elink1_txo_frame_n; // From elink1 of elink.v
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@ -159,9 +167,8 @@ module dv_elink(/*AUTOARG*/
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assign elink0_txrr_access = 1'b0;
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assign elink0_txrr_packet[PW-1:0] = 'b0;
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/*elink AUTO_TEMPLATE (
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/*elink AUTO_TEMPLATE (.reset (reset),
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// Outputs
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.hard_reset (reset),
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.clkbypass ({clkin,clkin,clkin}),
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.clkin (clkin),
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.sys_clk (clk[1]),
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@ -170,7 +177,7 @@ module dv_elink(/*AUTOARG*/
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*/
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defparam elink0.ID = 12'h810;
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elink elink0 (
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elink elink0 (.testmode (1'b0),//tie to 1 to enable
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.rxi_lclk_p (elink1_txo_lclk_p),
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.rxi_lclk_n (elink1_txo_lclk_n),
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.rxi_frame_p (elink1_txo_frame_p),
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@ -181,14 +188,10 @@ module dv_elink(/*AUTOARG*/
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.txi_wr_wait_n (elink1_rxo_wr_wait_n),
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.txi_rd_wait_p (elink1_rxo_rd_wait_p),
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.txi_rd_wait_n (elink1_rxo_rd_wait_n),
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/*AUTOINST*/
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// Outputs
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.colid (elink0_colid[3:0]), // Templated
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.rowid (elink0_rowid[3:0]), // Templated
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.chip_resetb (elink0_chip_resetb), // Templated
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.cclk_p (elink0_cclk_p), // Templated
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.cclk_n (elink0_cclk_n), // Templated
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.rx_lclk_div4 (elink0_rx_lclk_div4), // Templated
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.tx_lclk_div4 (elink0_tx_lclk_div4), // Templated
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.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
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@ -199,9 +202,10 @@ module dv_elink(/*AUTOARG*/
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.txo_frame_n (elink0_txo_frame_n), // Templated
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.txo_data_p (elink0_txo_data_p[7:0]), // Templated
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.txo_data_n (elink0_txo_data_n[7:0]), // Templated
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.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
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.mailbox_full (elink0_mailbox_full), // Templated
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.timeout (elink0_timeout), // Templated
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.chipid (elink0_chipid[11:0]), // Templated
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.chip_resetb (elink0_chip_resetb), // Templated
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.cclk_p (elink0_cclk_p), // Templated
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.cclk_n (elink0_cclk_n), // Templated
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.rxwr_access (elink0_rxwr_access), // Templated
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.rxwr_packet (elink0_rxwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink0_rxrd_access), // Templated
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@ -211,11 +215,14 @@ module dv_elink(/*AUTOARG*/
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.txwr_wait (elink0_txwr_wait), // Templated
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.txrd_wait (elink0_txrd_wait), // Templated
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.txrr_wait (elink0_txrr_wait), // Templated
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.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
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.mailbox_full (elink0_mailbox_full), // Templated
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.timeout (elink0_timeout), // Templated
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// Inputs
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.hard_reset (reset), // Templated
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.reset (reset), // Templated
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.clkin (clkin), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.sys_clk (clk[1]), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.rxwr_wait (elink0_rxwr_wait), // Templated
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.rxrd_wait (elink0_rxrd_wait), // Templated
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.rxrr_wait (elink0_rxrr_wait), // Templated
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@ -248,11 +255,8 @@ module dv_elink(/*AUTOARG*/
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.txi_rd_wait_n (elink0_rxo_rd_wait_n),
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/*AUTOINST*/
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// Outputs
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.colid (elink1_colid[3:0]), // Templated
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.rowid (elink1_rowid[3:0]), // Templated
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.chip_resetb (elink1_chip_resetb), // Templated
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.cclk_p (elink1_cclk_p), // Templated
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.cclk_n (elink1_cclk_n), // Templated
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.rx_lclk_div4 (elink1_rx_lclk_div4), // Templated
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.tx_lclk_div4 (elink1_tx_lclk_div4), // Templated
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.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
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@ -263,9 +267,10 @@ module dv_elink(/*AUTOARG*/
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.txo_frame_n (elink1_txo_frame_n), // Templated
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.txo_data_p (elink1_txo_data_p[7:0]), // Templated
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.txo_data_n (elink1_txo_data_n[7:0]), // Templated
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.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
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.mailbox_full (elink1_mailbox_full), // Templated
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.timeout (elink1_timeout), // Templated
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.chipid (elink1_chipid[11:0]), // Templated
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.chip_resetb (elink1_chip_resetb), // Templated
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.cclk_p (elink1_cclk_p), // Templated
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.cclk_n (elink1_cclk_n), // Templated
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.rxwr_access (elink1_rxwr_access), // Templated
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.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink1_rxrd_access), // Templated
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@ -275,11 +280,15 @@ module dv_elink(/*AUTOARG*/
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.txwr_wait (elink1_txwr_wait), // Templated
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.txrd_wait (elink1_txrd_wait), // Templated
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.txrr_wait (elink1_txrr_wait), // Templated
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.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
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.mailbox_full (elink1_mailbox_full), // Templated
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.timeout (elink1_timeout), // Templated
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// Inputs
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.hard_reset (reset), // Templated
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.reset (reset), // Templated
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.clkin (clkin), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.sys_clk (clk[1]), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.testmode (elink1_testmode), // Templated
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.rxwr_wait (elink1_rxwr_wait), // Templated
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.rxrd_wait (elink1_rxrd_wait), // Templated
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.rxrr_wait (elink1_rxrr_wait), // Templated
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@ -290,6 +299,54 @@ module dv_elink(/*AUTOARG*/
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.txrr_access (elink1_txrr_access), // Templated
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.txrr_packet (elink1_txrr_packet[PW-1:0])); // Templated
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elink_e16 elink2 (
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// Outputs
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.rxi_rd_wait (),
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.rxi_wr_wait (),
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.txo_data (),
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.txo_lclk (),
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.txo_frame (),
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.c0_mesh_access_out(),
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.c0_mesh_write_out (),
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.c0_mesh_dstaddr_out(),
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.c0_mesh_srcaddr_out(),
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.c0_mesh_data_out (),
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.c0_mesh_datamode_out(),
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.c0_mesh_ctrlmode_out(),
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.c0_emesh_wait_out (),
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.c0_mesh_wait_out (),
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// Inputs
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.reset (reset),
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.c0_clk_in (clk[1]),
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.c1_clk_in (clk[1]),
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.c2_clk_in (clk[1]),
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.c3_clk_in (clk[1]),
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.rxi_data (elink0_txo_data_p[7:0]),
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.rxi_lclk (elink0_txo_lclk_p),
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.rxi_frame (elink0_txo_frame_p),
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.txo_rd_wait (1'b0),
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.txo_wr_wait (1'b0),
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.c0_mesh_access_in (ext_access),
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.c0_mesh_write_in (ext_packet[1]),
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.c0_mesh_dstaddr_in(ext_packet[39:8]),
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.c0_mesh_srcaddr_in(ext_packet[103:72]),
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.c0_mesh_data_in (ext_packet[71:40]),
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.c0_mesh_datamode_in(ext_packet[3:2]),
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.c0_mesh_ctrlmode_in(ext_packet[7:4]),
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.c0_mesh_wait_in (1'b0),
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.c0_emesh_wait_in (1'b0),
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.c0_rdmesh_wait_in (1'b0),
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.c1_rdmesh_wait_in (1'b0),
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.c2_rdmesh_wait_in (1'b0),
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.c3_emesh_wait_in (1'b0),
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.c3_mesh_wait_in (1'b0),
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.c3_rdmesh_wait_in (1'b0),
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.txo_cfg_reg (6'b0)
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);
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assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) |
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@ -1,6 +1,7 @@
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../hdl/elink_constants.v
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../hdl/elink_regmap.v
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dv_elink_tb.v
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elink_e16_model.v
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-y .
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-y ../../elink/hdl
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-y ../../xilibs/hdl
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