From 094f417f66f5f20803598c10dc9e35b5a1d1bbe3 Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Fri, 3 Feb 2017 00:47:18 +0100 Subject: [PATCH] zcu102: Add package pins for FMC0 connector Signed-off-by: Ola Jeppsson --- src/zcu102/fpga/zcu102/system_params.tcl | 2 +- src/zcu102/fpga/zcu102_fmc0_io.xdc | 74 ++++++++++++++++++++++++ src/zcu102/fpga/zcu102_io.xdc | 58 ------------------- 3 files changed, 75 insertions(+), 59 deletions(-) create mode 100644 src/zcu102/fpga/zcu102_fmc0_io.xdc delete mode 100644 src/zcu102/fpga/zcu102_io.xdc diff --git a/src/zcu102/fpga/zcu102/system_params.tcl b/src/zcu102/fpga/zcu102/system_params.tcl index 485d72f..f45936b 100644 --- a/src/zcu102/fpga/zcu102/system_params.tcl +++ b/src/zcu102/fpga/zcu102/system_params.tcl @@ -18,7 +18,7 @@ set hdl_files [] #All constraints files set constraints_files [list \ ../zcu102_timing.xdc \ - ../zcu102_io.xdc \ + ../zcu102_fmc0_io.xdc \ ] ########################################################### diff --git a/src/zcu102/fpga/zcu102_fmc0_io.xdc b/src/zcu102/fpga/zcu102_fmc0_io.xdc new file mode 100644 index 0000000..795c5d6 --- /dev/null +++ b/src/zcu102/fpga/zcu102_fmc0_io.xdc @@ -0,0 +1,74 @@ +####################### +# Configuration Pins +####################### +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +##################### +# Epiphany Reset +# Schematic RESETB +##################### +set_property IOSTANDARD LVCMOS25 [get_ports {chip_nreset}] +set_property PACKAGE_PIN AC7 [get_ports {chip_nreset}] + +########################## +# AD9523 clock power down +# (active low) +# Schematic CLKPD_1P8V +########################## +set_property IOSTANDARD LVCMOS18 [get_ports {clkpd_1p8v}] +set_property PACKAGE_PIN AC6 [get_ports {clkpd_1p8v}] + +##################### +# Epiphany Clocks (Tile 0-7) +# Schematic CLKIN_[PN]01 +# Connected to clock distributor chip. +# Assume pass through will work. +##################### +set_property IOSTANDARD LVDS_25 [get_ports {cclk*}] +# (Tile 0-7) +set_property PACKAGE_PIN W6 [get_ports cclk0_n] +# (Tile 8-15) +set_property PACKAGE_PIN AA12 [get_ports cclk1_n] + +######################### +# FPGA Elink TX (chip RX) +######################### +set_property IOSTANDARD LVDS_25 [get_ports {txo*}] +set_property IOSTANDARD LVDS_25 [get_ports {txi*}] +set_property PACKAGE_PIN N11 [get_ports txo_lclk_n] +set_property PACKAGE_PIN N8 [get_ports {txo_data_n[0]}] +set_property PACKAGE_PIN K13 [get_ports {txo_data_n[1]}] +set_property PACKAGE_PIN M13 [get_ports {txo_data_n[2]}] +set_property PACKAGE_PIN N12 [get_ports {txo_data_n[3]}] +set_property PACKAGE_PIN M14 [get_ports {txo_data_n[4]}] +set_property PACKAGE_PIN K16 [get_ports {txo_data_n[5]}] +set_property PACKAGE_PIN K12 [get_ports {txo_data_n[6]}] +set_property PACKAGE_PIN L11 [get_ports {txo_data_n[7]}] +set_property PACKAGE_PIN K15 [get_ports txo_frame_n] +set_property PACKAGE_PIN T6 [get_ports txi_wr_wait_n] + +##################### +# Wait signals +##################### +# ??? Parallella board has LVCMOS25 and a DIFF LINE RECEIVER +set_property IOSTANDARD LVCMOS25 [get_ports {txi_rd_wait_*}] +set_property PACKAGE_PIN L10 [get_ports txi_rd_wait_n] + + +######################### +# FPGA ELink RX (chip TX) +######################### +set_property IOSTANDARD LVDS_25 [get_ports {rx*}] +set_property PACKAGE_PIN Y3 [get_ports rxi_lclk_n] +set_property PACKAGE_PIN AC4 [get_ports {rxi_data_n[0]}] +set_property PACKAGE_PIN V1 [get_ports {rxi_data_n[1]}] +set_property PACKAGE_PIN Y2 [get_ports {rxi_data_n[2]}] +set_property PACKAGE_PIN AA1 [get_ports {rxi_data_n[3]}] +set_property PACKAGE_PIN AC3 [get_ports {rxi_data_n[4]}] +set_property PACKAGE_PIN AC1 [get_ports {rxi_data_n[5]}] +set_property PACKAGE_PIN U4 [get_ports {rxi_data_n[6]}] +set_property PACKAGE_PIN V3 [get_ports {rxi_data_n[7]}] +set_property PACKAGE_PIN V3 [get_ports rxi_frame_n] +set_property PACKAGE_PIN W1 [get_ports rxo_rd_wait_n] +set_property PACKAGE_PIN AB5 [get_ports rxo_wr_wait_n] diff --git a/src/zcu102/fpga/zcu102_io.xdc b/src/zcu102/fpga/zcu102_io.xdc deleted file mode 100644 index a7a3d5f..0000000 --- a/src/zcu102/fpga/zcu102_io.xdc +++ /dev/null @@ -1,58 +0,0 @@ -####################### -# Configuration Pins -####################### -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] - -##################### -# Epiphany Reset -##################### -set_property IOSTANDARD LVCMOS25 [get_ports {chip_nreset}] -set_property PACKAGE_PIN G14 [get_ports {chip_nreset}] - -##################### -# Epiphany Clock -##################### -set_property IOSTANDARD LVDS_25 [get_ports {cclk*}] -set_property PACKAGE_PIN H17 [get_ports cclk_n] - -##################### -# Epiphany TX -##################### -set_property IOSTANDARD LVDS_25 [get_ports {txo*}] -set_property IOSTANDARD LVDS_25 [get_ports {txi*}] -set_property PACKAGE_PIN F17 [get_ports txo_lclk_n] -set_property PACKAGE_PIN A20 [get_ports {txo_data_n[0]}] -set_property PACKAGE_PIN B20 [get_ports {txo_data_n[1]}] -set_property PACKAGE_PIN D20 [get_ports {txo_data_n[2]}] -set_property PACKAGE_PIN E19 [get_ports {txo_data_n[3]}] -set_property PACKAGE_PIN D18 [get_ports {txo_data_n[4]}] -set_property PACKAGE_PIN F20 [get_ports {txo_data_n[5]}] -set_property PACKAGE_PIN G18 [get_ports {txo_data_n[6]}] -set_property PACKAGE_PIN G20 [get_ports {txo_data_n[7]}] -set_property PACKAGE_PIN G15 [get_ports txo_frame_n] -set_property PACKAGE_PIN H18 [get_ports txi_wr_wait_n] - -##################### -# Wait signals -##################### -set_property IOSTANDARD LVCMOS25 [get_ports {txi_rd_wait_*}] -set_property PACKAGE_PIN J15 [get_ports txi_rd_wait_p] - - -##################### -# Epiphany RX -##################### -set_property IOSTANDARD LVDS_25 [get_ports {rx*}] -set_property PACKAGE_PIN K18 [get_ports rxi_lclk_n] -set_property PACKAGE_PIN J19 [get_ports {rxi_data_n[0]}] -set_property PACKAGE_PIN L15 [get_ports {rxi_data_n[1]}] -set_property PACKAGE_PIN L17 [get_ports {rxi_data_n[2]}] -set_property PACKAGE_PIN M15 [get_ports {rxi_data_n[3]}] -set_property PACKAGE_PIN L20 [get_ports {rxi_data_n[4]}] -set_property PACKAGE_PIN M20 [get_ports {rxi_data_n[5]}] -set_property PACKAGE_PIN M18 [get_ports {rxi_data_n[6]}] -set_property PACKAGE_PIN N16 [get_ports {rxi_data_n[7]}] -set_property PACKAGE_PIN H20 [get_ports rxi_frame_n] -set_property PACKAGE_PIN J14 [get_ports rxo_rd_wait_n] -set_property PACKAGE_PIN J16 [get_ports rxo_wr_wait_n]