Adding wrappers for pnr

src/chip/pnr/01_setup.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/01_setup.tcl
+

src/chip/pnr/02_netlist.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/02_netlist.tcl
+

src/chip/pnr/03_constrain.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/03_constrain.tcl
+

src/chip/pnr/04_floorplan.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/04_floorplan.tcl

src/chip/pnr/05_place.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/05_place.tcl

src/chip/pnr/06_clock.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/06_clock.tcl
+

src/chip/pnr/07_route.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/07_route.tcl
+

src/chip/pnr/08_cleanup.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/08_cleanup.tcl
+

src/chip/pnr/09_signoff.tcl

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+source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/09_signoff.tcl
+

src/chip/pnr/README.md

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-## Content
-- standard setup/run files for tools like ICC 
+OH!: Place and Route Flow
+=====================================
+
+This guide documents the OH! back end place and route flow that takes the design from netlist to GDS. The flow requires certain TCL and Shell variables to be setup, as defined [HERE](../README.md).
+
+The synthesis flow scripts call EDA specific scipts as needed. 
+
+# SYNTHESIS FLOW
+
+| FILE                   | NOTES                                       |
+|------------------------|---------------------------------------------| 
+| 01_setup_tool.tcl      | Setup synthesis tool                        | 
+| 02_read_design.tcl     | Read in design files                        | 
+| 03_read_constraints.tcl| Read in design constaints                   | 
+| 04_setup_corners.tcl   | Setup up operating conditions               | 
+| 05_floorplan.tcl       | Read floorplan information                  | 
+| 06_check_design.tcl    | Check design integrity                      | 
+| 07_compile.tcl         | Comile HDL to gates                         | 
+| 08_dft.tcl             | Insert test features (scan)                 | 
+| 09_optimize.tcl        | Seconday optimization step                  | 
+| 10_write_netlist.tcl   | Write out netlists and reports              | 
+                
+## Example Setup File ("example.tcl")
+
+```tcl
+set OH_VENDOR     "synopsys"
+
+set OH_TOOl       "icc"
+
+set OH_DESIGN     "ecore"
+
+set OH_LIBS       "svtlib"
+
+set OH_MACROS     "sram64x1024"
+
+set OH_FILES      "../../../hdl/$OH_DESIGN.v             \
+                   -y $env(OH_HOME)/emesh/hdl            \
+                   -y $env(OH_HOME)/common/hdl           \
+                   -y $env(EPIPHANY_HOME)/chip/hdl       \
+                   -y $env(EPIPHANY_HOME)/ecore/hdl      \
+                   -y $env(EPIPHANY_HOME)/emesh/hdl      \
+                   -y $env(EPIPHANY_HOME)/edma/hdl       \
+                   -y $env(EPIPHANY_HOME)/compute/hdl    \
+                   -y $env(EPIPHANY_HOME)/memory/hdl     \
+                   -y $env(EPIPHANY_HOME)/fpumm/hdl      \
+                   +incdir+$env(EPIPHANY_HOME)/emesh/hdl \
+                   +incdir+$env(EPIPHANY_HOME)/ecore/hdl \
+                   +incdir+$env(EPIPHANY_HOME)/edma/hdl"
+
+set OH_CONSTRAINTS  "${OH_DESIGN}.sdc"
+
+set OH_FLOORPLAN    "${OH_DESIGN}_floorplan.tcl"
+
+```
+
+## Usage
+
+```
+>> cd 
+>> dc_shell -topographical_mode
+dc_shell> source $env(OH_HOME)/chip/synthesis/example.tcl
+```

src/chip/pnr/defaults.tcl

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+#################################
+# PROCESS/LIBS DEFAULTS (SHELL)
+#################################
+
+if {[info exists env(OH_VENDOR)]} {
+    set OH_VENDOR  "$env(OH_VENDOR)"; # synopsys, cadence, xilinx
+}
+
+if {[info exists env(OH_TARGET)]} {
+    set OH_TARGET  "$env(OH_TARGET)"; # "lib1.db lib2.db lib3.db" or "xc7z020clg400-1"
+}
+
+if {[info exists env(OH_MACROS)]} {
+    set OH_MACROS  "$env(OH_MACROS)"; # "macro1.lib macro2.lib"
+}

src/chip/pnr/example.tcl

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+set LOCALPATH [file dirname [ info script ]]
+
+######################################
+# DESIGN SPECIFIC 
+######################################
+
+set OH_DESIGN     "ecore"
+
+set OH_FILES      "../../../hdl/$OH_DESIGN.v             \
+                   -y $env(OH_HOME)/emesh/hdl            \
+                   -y $env(OH_HOME)/common/hdl           \
+                   -y $env(EPIPHANY_HOME)/chip/hdl       \
+                   -y $env(EPIPHANY_HOME)/ecore/hdl      \
+                   -y $env(EPIPHANY_HOME)/emesh/hdl      \
+                   -y $env(EPIPHANY_HOME)/edma/hdl       \
+                   -y $env(EPIPHANY_HOME)/compute/hdl    \
+                   -y $env(EPIPHANY_HOME)/memory/hdl     \
+                   -y $env(EPIPHANY_HOME)/fpumm/hdl      \
+                   +incdir+$env(EPIPHANY_HOME)/emesh/hdl \
+                   +incdir+$env(EPIPHANY_HOME)/ecore/hdl \
+                   +incdir+$env(EPIPHANY_HOME)/edma/hdl"
+
+set OH_CONSTRAINTS  "${OH_DESIGN}.sdc"
+
+set OH_FLOORPLAN    "${OH_DESIGN}_floorplan.tcl"
+
+set OH_LIBS       "svtlib lvtlib";      # ip library names 
+
+set OH_MACROS     "sram_macro";         # hard macro library names
+ 
+set OH_VENDOR     "synopsys";           # eda vendor name   
+
+set OH_TOOL       "dc";                 # name of eda vendor synthesis tool
+
+######################################
+# RUN SYNTHESIS
+#####################################
+source  $LOCALPATH/run.tcl
+

src/chip/pnr/run.tcl

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+#SET PATH
+set LOCALPATH [file dirname [ info script ]]
+
+################################
+# SETUP PROCESS
+################################
+
+source $env(PROCESS_HOME)/eda/$OH_VENDOR/setup_process.tcl
+
+################################
+# CHECK ENVIRONMENT VARIABLES
+################################
+
+set OH_VENDOR "synopsys"
+set OH_MACROS ""
+set OH_TARGET ""
+
+if {[string match synopsys $OH_VENDOR]} {
+    set OH_TOOL "dc"
+} elseif {[string match cadence $OH_VENDOR]} {
+    set OH_TOOL "rc"
+} elseif {[string match xilinx $OH_VENDOR]} {
+    set OH_TOOL "vivado"
+}
+
+# Check that all variabls are defined
+# If not defined exit!
+puts $OH_DESIGN
+puts $OH_TOP
+puts $OH_CFG
+puts $OH_LIBS
+puts $OH_FLOORPLAN
+puts $OH_VENDOR
+puts $OH_TOOL
+puts $OH_TARGET
+puts $OH_MACROS
+puts $OH_LAYER_MIN
+puts $OH_LAYER_MAX
+puts $OH_LIBPATH
+puts $OH_TECHFILE
+puts $OH_MAP
+puts $OH_RCMODEL_MAX
+puts $OH_RCMODEL_MIN
+
+################################
+# STEP1: SETUP TOOL
+################################
+
+source $LOCALPATH/01_setup.tcl
+
+################################
+# STEP2: READ NETLIST
+################################
+
+source $LOCALPATH/02_nelist.tcl
+
+################################
+# STEP3: CONSTRAIN DESIGN
+################################
+
+source $LOCALPATH/03_constrain.tcl
+
+################################
+# STEP4: READ FLOORPLAN
+################################
+
+source $LOCALPATH/04_floorplan.tcl
+
+################################
+# STEP5: PLACE DESIGN
+################################
+
+source $LOCALPATH/05_place.tcl
+
+################################
+# STEP6: CLOCKS
+################################
+
+source $LOCALPATH/06_clock.tcl
+
+################################
+# STEP7: ROUTE
+################################
+
+source $LOCALPATH/07_route.tcl
+
+################################
+# STEP8: CLEANUP
+################################
+
+source $LOCALPATH/08_cleanup.tcl
+
+################################
+# STEP8: SIGNOFF
+################################
+
+source $LOCALPATH/09_signoff.tcl
+
+#exit
+