mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
Andreas Olofsson
commit
0a381ccffe
33
Makefile.in
Normal file
33
Makefile.in
Normal file
@ -0,0 +1,33 @@
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have_vivado := $(shell which vivado 1>/dev/null 2>/dev/null && echo yes)
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top_srcdir := @top_srcdir@
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top_builddir := @top_builddir@
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export
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.PHONY: builddeps all parallella-16-nohdmi clean
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help:
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@echo "TARGETS:"
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@echo "all -- everything (TODO)"
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@echo "parallella-z7020 -- Parallella Embedded (no HDMI)"
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builddeps:
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@if [ "x$(have_vivado)" != "xyes" ]; then echo vivado not in path; exit 1; fi
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all: builddeps parallella-z7020
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# TODO
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parallella-z7020: builddeps
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vivado -mode batch -source $(top_srcdir)/projects/parallella-z7020/system_project.tcl
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# Temporary
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package_axi_elink: builddeps
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vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/package_axi_elink.tcl
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# Temporary
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elink: builddeps
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vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/run.tcl
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clean:
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find . \( -name "vivado*.log" -or -name "vivado*.jou" \) -delete
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13
README.md
13
README.md
@ -2,4 +2,15 @@
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# OH!
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Open Hardware (Pure and Simple)
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(work in progress...)
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(work in progress...)
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## Building
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```
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git clone https://github.com/parallella/oh.git
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cd oh
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mkdir build
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cd build
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../configure
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make elink
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```
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12
configure
vendored
Executable file
12
configure
vendored
Executable file
@ -0,0 +1,12 @@
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#!/bin/bash
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if ! which vivado 1>/dev/null; then
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echo ERROR: Vivado not in PATH
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echo 'Try "source /opt/Xilinx/Vivado/201X.X/settings.sh"'
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exit 1
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fi
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top_srcdir=$(dirname $(readlink -f "$0"))
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top_builddir=$(pwd)
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sed "s|@top_srcdir@|${top_srcdir}|g;s|@top_builddir@|${top_builddir}|g" \
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< $top_srcdir/Makefile.in > $top_builddir/Makefile
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@ -1,46 +1,29 @@
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########################################################
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set oh_path "../.."
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set pwd [file dirname [info script]]
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source $pwd/../../../include/oh.tcl
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# ???
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set_msg_config -id {ip_flow 19-459} -suppress
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########################################################
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#create a project
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set block axi_elink
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create_project $block . -force
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oh::ip::create axi_elink $top_builddir/axi_elink
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#######################################################
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#add files
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add_files -norecurse $oh_path/common/hdl
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add_files -norecurse $oh_path/emesh/hdl
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add_files -norecurse $oh_path/emmu/hdl/emmu.v
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add_files -norecurse $oh_path/edma/hdl/edma.v
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add_files -norecurse $oh_path/emailbox/hdl/emailbox.v
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add_files -norecurse $oh_path/elink/hdl
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set elink_src_files [list \
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"$top_srcdir/common/hdl" \
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"$top_srcdir/emesh/hdl" \
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"$top_srcdir/emmu/hdl/emmu.v" \
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"$top_srcdir/edma/hdl/edma.v" \
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"$top_srcdir/emailbox/hdl/emailbox.v" \
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"$top_srcdir/elink/hdl" ]
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set elink_constr_files [list \
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"$top_srcdir/elink/scripts/xilinx/elink_clocks.xdc" \
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"$top_srcdir/elink/scripts/xilinx/elink_pins.xdc" \
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"$top_srcdir/elink/scripts/xilinx/elink_timing.xdc" ]
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set elink_ip_files [concat $elink_src_files $elink_constr_files]
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#######################################################
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#Package IP
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ipx::package_project -root_dir .
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oh::ip::add_files axi_elink $elink_ip_files
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# Does not work / is it needed ?
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#oh::ip::add_constraints $elink_constr_files
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#######################################################
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#Vendor settings
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set_property vendor {www.parallella.org} [ipx::current_core]
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set_property library {user} [ipx::current_core]
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set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
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set_property vendor_display_name {OH!} [ipx::current_core]
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set_property company_url {www.parallella.org} [ipx::current_core]
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oh::ip::set_properties $top_builddir/axi_elink
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#######################################################
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#Device Families Supported
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set_property supported_families \
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{
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{virtex7} {Production} \
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{kintex7} {Production} \
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{artix7} {Production} \
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{zynq} {Production}} \
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[ipx::current_core]
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#######################################################
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#Save files
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ipx::save_core [ipx::current_core]
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@ -1,5 +1,10 @@
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set SRC /home/aolofsson/Work_all/oh
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read_xdc $SRC/elink/syn/xilinx/elink_pins.xdc
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read_xdc $SRC/elink/syn/xilinx/elink_timing.xdc
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set pwd [file dirname [info script]]
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source $pwd/../../../include/oh.tcl
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read_xdc $pwd/elink_pins.xdc
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read_xdc $pwd/elink_timing.xdc
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# Do we need this?
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#read_xdc $pwd/elink_clocks.xdc
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@ -1,3 +1,6 @@
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read_ip ../../../xilibs/ip/fifo_async_104x16.xci
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set pwd [file dirname [info script]]
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source $pwd/../../../include/oh.tcl
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read_ip $top_srcdir/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci
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read_ip $top_srcdir/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci
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@ -1,54 +1,58 @@
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set SRC /home/aolofsson/Work_all/oh
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set pwd [file dirname [info script]]
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source $pwd/../../../include/oh.tcl
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#ONLY FOR REFERENCE EXAMPLE
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read_verilog $SRC/elink/hdl/axi_elink.v
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read_verilog $top_srcdir/elink/hdl/axi_elink.v
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#ELINK
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read_verilog $SRC/elink/hdl/elink_constants.v
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read_verilog $SRC/elink/hdl/elink_regmap.v
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read_verilog $SRC/elink/hdl/elink.v
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read_verilog $SRC/elink/hdl/eclocks.v
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read_verilog $SRC/elink/hdl/ereset.v
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read_verilog $SRC/elink/hdl/ecfg_elink.v
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read_verilog $SRC/elink/hdl/ecfg_if.v
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read_verilog $SRC/elink/hdl/erx.v
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read_verilog $SRC/elink/hdl/erx_core.v
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read_verilog $SRC/elink/hdl/erx_fifo.v
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read_verilog $SRC/elink/hdl/erx_cfg.v
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read_verilog $SRC/elink/hdl/erx_arbiter.v
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read_verilog $SRC/elink/hdl/erx_protocol.v
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read_verilog $SRC/elink/hdl/erx_remap.v
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read_verilog $SRC/elink/hdl/erx_io.v
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read_verilog $SRC/elink/hdl/etx.v
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read_verilog $SRC/elink/hdl/etx_core.v
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read_verilog $SRC/elink/hdl/etx_fifo.v
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read_verilog $SRC/elink/hdl/etx_cfg.v
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read_verilog $SRC/elink/hdl/etx_arbiter.v
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read_verilog $SRC/elink/hdl/etx_protocol.v
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read_verilog $SRC/elink/hdl/etx_remap.v
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read_verilog $SRC/elink/hdl/etx_io.v
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read_verilog $top_srcdir/elink/hdl/elink_constants.v
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read_verilog $top_srcdir/elink/hdl/elink_regmap.v
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read_verilog $top_srcdir/elink/hdl/elink.v
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read_verilog $top_srcdir/elink/hdl/eclocks.v
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read_verilog $top_srcdir/elink/hdl/ereset.v
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read_verilog $top_srcdir/elink/hdl/ecfg_elink.v
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read_verilog $top_srcdir/elink/hdl/ecfg_if.v
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read_verilog $top_srcdir/elink/hdl/erx.v
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read_verilog $top_srcdir/elink/hdl/erx_core.v
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read_verilog $top_srcdir/elink/hdl/erx_fifo.v
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read_verilog $top_srcdir/elink/hdl/erx_cfg.v
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read_verilog $top_srcdir/elink/hdl/erx_arbiter.v
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read_verilog $top_srcdir/elink/hdl/erx_protocol.v
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read_verilog $top_srcdir/elink/hdl/erx_remap.v
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read_verilog $top_srcdir/elink/hdl/erx_io.v
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read_verilog $top_srcdir/elink/hdl/etx.v
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read_verilog $top_srcdir/elink/hdl/etx_core.v
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read_verilog $top_srcdir/elink/hdl/etx_fifo.v
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read_verilog $top_srcdir/elink/hdl/etx_cfg.v
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read_verilog $top_srcdir/elink/hdl/etx_arbiter.v
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read_verilog $top_srcdir/elink/hdl/etx_protocol.v
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read_verilog $top_srcdir/elink/hdl/etx_remap.v
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read_verilog $top_srcdir/elink/hdl/etx_io.v
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read_verilog $top_srcdir/elink/hdl/esaxi.v
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read_verilog $top_srcdir/elink/hdl/emaxi.v
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#COMMON
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read_verilog $SRC/common/hdl/toggle2pulse.v
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read_verilog $SRC/common/hdl/synchronizer.v
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read_verilog $SRC/common/hdl/pulse_stretcher.v
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read_verilog $SRC/common/hdl/clock_divider.v
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read_verilog $SRC/common/hdl/arbiter_priority.v
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read_verilog $top_srcdir/common/hdl/toggle2pulse.v
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read_verilog $top_srcdir/common/hdl/synchronizer.v
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read_verilog $top_srcdir/common/hdl/pulse_stretcher.v
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read_verilog $top_srcdir/common/hdl/clock_divider.v
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read_verilog $top_srcdir/common/hdl/arbiter_priority.v
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#EMESH
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read_verilog $SRC/emesh/hdl/emesh2packet.v
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read_verilog $SRC/emesh/hdl/packet2emesh.v
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read_verilog $top_srcdir/emesh/hdl/emesh2packet.v
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read_verilog $top_srcdir/emesh/hdl/packet2emesh.v
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#MEMORY/FIFO
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read_verilog $SRC/memory/hdl/fifo_async.v
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read_verilog $SRC/memory/hdl/fifo_cdc.v
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read_verilog $SRC/memory/hdl/memory_dp.v
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read_verilog $SRC/memory/hdl/memory_sp.v
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read_verilog $SRC/memory/hdl/fifo_full_block.v
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read_verilog $SRC/memory/hdl/fifo_empty_block.v
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read_verilog $top_srcdir/memory/hdl/fifo_async.v
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read_verilog $top_srcdir/memory/hdl/fifo_sync.v
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read_verilog $top_srcdir/memory/hdl/fifo_cdc.v
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read_verilog $top_srcdir/memory/hdl/memory_dp.v
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read_verilog $top_srcdir/memory/hdl/memory_sp.v
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read_verilog $top_srcdir/memory/hdl/fifo_full_block.v
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read_verilog $top_srcdir/memory/hdl/fifo_empty_block.v
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#MMU
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read_verilog $SRC/emmu/hdl/emmu.v
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read_verilog $SRC/emailbox/hdl/emailbox.v
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read_verilog $SRC/edma/hdl/edma.v
|
||||
read_verilog $top_srcdir/emmu/hdl/emmu.v
|
||||
read_verilog $top_srcdir/emailbox/hdl/emailbox.v
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||||
read_verilog $top_srcdir/edma/hdl/edma.v
|
||||
|
||||
|
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@ -1,17 +1,20 @@
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set pwd [file dirname [info script]]
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source $pwd/../../../include/oh.tcl
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||||
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###########################################################
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#STEP0: Define variables
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||||
set OUTDIR ./tmp
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set PART xc7z010clg400-1
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set TOP elink_example
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set TOP axi_elink
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file mkdir $OUTDIR
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###########################################################
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#STEP1: Read sources, constraints, IP files
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create_project -in_memory -part $PART -force my_project
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source read_verilog.tcl
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source read_constraints.tcl
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source read_ip.tcl
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||||
source $pwd/read_verilog.tcl
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||||
source $pwd/read_constraints.tcl
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||||
source $pwd/read_ip.tcl
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||||
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###########################################################
|
||||
#STEP2: SYNTHESIS
|
||||
@ -79,12 +82,3 @@ write_verilog -force $OUTDIR/$TOP.v
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write_xdc -no_fixed_only -force $OUTDIR/$TOP.xdc
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write_bitstream -force $OUTDIR/$TOP.bit
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
63
include/oh.tcl
Normal file
63
include/oh.tcl
Normal file
@ -0,0 +1,63 @@
|
||||
set top_srcdir [file dirname [info script]]/..
|
||||
set top_builddir $top_srcdir
|
||||
|
||||
# Alias, some scripts use this atm.
|
||||
# TODO: Remove
|
||||
set oh_path $top_srcdir
|
||||
|
||||
# TODO: Support building out of tree
|
||||
if [info exists ::env(top_builddir)] {
|
||||
set top_builddir $::env(top_builddir)
|
||||
}
|
||||
|
||||
namespace eval oh {
|
||||
namespace eval ip {
|
||||
|
||||
proc create {ip_name ip_dir} {
|
||||
# ::create_project $ip_name $ip_dir -force
|
||||
::create_project -in_memory
|
||||
|
||||
::update_ip_catalog
|
||||
}
|
||||
|
||||
proc add_files {ip_name ip_files} {
|
||||
set fileset [::get_filesets sources_1]
|
||||
::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files
|
||||
::set_property "top" "$ip_name" $fileset
|
||||
}
|
||||
|
||||
# TODO: Does not work. filegroup is empty
|
||||
proc add_constraints {ip_constr_files {processing_order late}} {
|
||||
# set filegroup [::ipx::get_file_groups xilinx_v*synthesis -of_objects [::ipx::current_core]]
|
||||
# puts $filegroup
|
||||
# set f [::ipx::add_file $ip_constr_files $filegroup]
|
||||
# ::set_property -dict \
|
||||
# [list \
|
||||
# type xdc \
|
||||
# library_name {} \
|
||||
# processing_order $processing_order \
|
||||
# ] \
|
||||
# $f
|
||||
}
|
||||
|
||||
proc set_properties {ip_dir} {
|
||||
set c ::ipx::current_core
|
||||
::ipx::package_project -root_dir $ip_dir
|
||||
::set_property vendor {www.parallella.org} [$c]
|
||||
::set_property library {user} [$c]
|
||||
::set_property taxonomy {{/AXI_Infrastructure}} [$c]
|
||||
::set_property vendor_display_name {OH!} [$c]
|
||||
::set_property company_url {www.parallella.org} [$c]
|
||||
|
||||
::set_property supported_families \
|
||||
{
|
||||
{virtex7} {Production} \
|
||||
{kintex7} {Production} \
|
||||
{artix7} {Production} \
|
||||
{zynq} {Production} \
|
||||
} \
|
||||
[$c]
|
||||
}
|
||||
|
||||
}; # namespace ip
|
||||
}; # namespace oh
|
||||
@ -32,7 +32,8 @@ update_ip_catalog -rebuild
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
set files [list \
|
||||
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x16.xci"]"\
|
||||
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"]"\
|
||||
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"]"\
|
||||
"[file normalize "$oh_path/memory/hdl/fifo_async.v"]"\
|
||||
"[file normalize "$oh_path/memory/hdl/memory_dp.v"]"\
|
||||
"[file normalize "$oh_path/emesh/hdl/packet2emesh.v"]"\
|
||||
@ -76,7 +77,7 @@ set files [list \
|
||||
add_files -norecurse -fileset $obj $files
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
set file "$oh_path/xilibs/ip/fifo_async_104x16.xci"
|
||||
set file "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
@ -84,6 +85,17 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
}
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
set file "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property "synth_checkpoint_mode" "Singular" $file_obj
|
||||
}
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
|
||||
|
||||
set file "$oh_path/memory/hdl/fifo_async.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user