From 11307d072f409cd6920f4f9d18e52de55970f172 Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 19:40:30 +0200 Subject: [PATCH 1/7] Add ip generation helper script Signed-off-by: Ola Jeppsson --- include/oh.tcl | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 include/oh.tcl diff --git a/include/oh.tcl b/include/oh.tcl new file mode 100644 index 0000000..b9afccc --- /dev/null +++ b/include/oh.tcl @@ -0,0 +1,63 @@ +set top_srcdir [file dirname [info script]]/.. +set top_builddir $top_srcdir + +# Alias, some scripts use this atm. +# TODO: Remove +set oh_path $top_srcdir + +# TODO: Support building out of tree +if [info exists ::env(top_builddir)] { + set top_builddir $::env(top_builddir) +} + +namespace eval oh { +namespace eval ip { + +proc create {ip_name ip_dir} { +# ::create_project $ip_name $ip_dir -force + ::create_project -in_memory + + ::update_ip_catalog +} + +proc add_files {ip_name ip_files} { + set fileset [::get_filesets sources_1] + ::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files + ::set_property "top" "$ip_name" $fileset +} + +# TODO: Does not work. filegroup is empty +proc add_constraints {ip_constr_files {processing_order late}} { +# set filegroup [::ipx::get_file_groups xilinx_v*synthesis -of_objects [::ipx::current_core]] +# puts $filegroup +# set f [::ipx::add_file $ip_constr_files $filegroup] +# ::set_property -dict \ +# [list \ +# type xdc \ +# library_name {} \ +# processing_order $processing_order \ +# ] \ +# $f +} + +proc set_properties {ip_dir} { + set c ::ipx::current_core + ::ipx::package_project -root_dir $ip_dir + ::set_property vendor {www.parallella.org} [$c] + ::set_property library {user} [$c] + ::set_property taxonomy {{/AXI_Infrastructure}} [$c] + ::set_property vendor_display_name {OH!} [$c] + ::set_property company_url {www.parallella.org} [$c] + + ::set_property supported_families \ + { + {virtex7} {Production} \ + {kintex7} {Production} \ + {artix7} {Production} \ + {zynq} {Production} \ + } \ + [$c] +} + +}; # namespace ip +}; # namespace oh From d03e70a016d8d43a9ddd311cda5276b80a1082b8 Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 19:43:01 +0200 Subject: [PATCH 2/7] Add Makefile Signed-off-by: Ola Jeppsson --- Makefile | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Makefile diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..b5102ce --- /dev/null +++ b/Makefile @@ -0,0 +1,27 @@ +have_vivado := $(shell which vivado 1>/dev/null 2>/dev/null && echo yes) +top_srcdir := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +top_builddir := $(shell pwd) + +export + +.PHONY: builddeps all parallella-16-nohdmi clean + +help: + @echo "TARGETS:" + @echo "all -- everything (TODO)" + @echo "parallella-z7020 -- Parallella Embedded (no HDMI)" + +builddeps: + @if [ "x$(have_vivado)" != "xyes" ]; then echo vivado not in path; exit 1; fi + +all: builddeps parallella-z7020 + +parallella-z7020: builddeps + make -C targets/parallella-z7020/Makefile +# vivado -mode batch -source targets/parallella-z7020/system_project.tcl + +test: + vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/package_axi_elink.tcl + +clean: + find . \( -name vivado*.log -or -name vivado*.jou \) -delete From 3db4e496755da82ea621e867f4adadd06864a7a5 Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 19:43:32 +0200 Subject: [PATCH 3/7] elink: Convert package_axi_elink to use helper script Signed-off-by: Ola Jeppsson --- elink/scripts/xilinx/package_axi_elink.tcl | 57 ++++++++-------------- 1 file changed, 20 insertions(+), 37 deletions(-) diff --git a/elink/scripts/xilinx/package_axi_elink.tcl b/elink/scripts/xilinx/package_axi_elink.tcl index 166a503..0ffa3ef 100644 --- a/elink/scripts/xilinx/package_axi_elink.tcl +++ b/elink/scripts/xilinx/package_axi_elink.tcl @@ -1,46 +1,29 @@ -######################################################## -set oh_path "../.." +set pwd [file dirname [info script]] +source $pwd/../../../include/oh.tcl +# ??? set_msg_config -id {ip_flow 19-459} -suppress -######################################################## -#create a project -set block axi_elink -create_project $block . -force +oh::ip::create axi_elink $top_builddir/axi_elink -####################################################### -#add files -add_files -norecurse $oh_path/common/hdl -add_files -norecurse $oh_path/emesh/hdl -add_files -norecurse $oh_path/emmu/hdl/emmu.v -add_files -norecurse $oh_path/edma/hdl/edma.v -add_files -norecurse $oh_path/emailbox/hdl/emailbox.v -add_files -norecurse $oh_path/elink/hdl +set elink_src_files [list \ + "$top_srcdir/common/hdl" \ + "$top_srcdir/emesh/hdl" \ + "$top_srcdir/emmu/hdl/emmu.v" \ + "$top_srcdir/edma/hdl/edma.v" \ + "$top_srcdir/emailbox/hdl/emailbox.v" \ + "$top_srcdir/elink/hdl" ] +set elink_constr_files [list \ + "$top_srcdir/elink/scripts/xilinx/elink_clocks.xdc" \ + "$top_srcdir/elink/scripts/xilinx/elink_pins.xdc" \ + "$top_srcdir/elink/scripts/xilinx/elink_timing.xdc" ] +set elink_ip_files [concat $elink_src_files $elink_constr_files] -####################################################### -#Package IP -ipx::package_project -root_dir . +oh::ip::add_files axi_elink $elink_ip_files +# Does not work / is it needed ? +#oh::ip::add_constraints $elink_constr_files -####################################################### -#Vendor settings -set_property vendor {www.parallella.org} [ipx::current_core] -set_property library {user} [ipx::current_core] -set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] -set_property vendor_display_name {OH!} [ipx::current_core] -set_property company_url {www.parallella.org} [ipx::current_core] +oh::ip::set_properties $top_builddir/axi_elink -####################################################### -#Device Families Supported -set_property supported_families \ - { - {virtex7} {Production} \ - {kintex7} {Production} \ - {artix7} {Production} \ - {zynq} {Production}} \ - [ipx::current_core] - -####################################################### -#Save files ipx::save_core [ipx::current_core] - From 47fe8ff92386016e1c497b71d842a78ad6a03e4f Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 23:30:55 +0200 Subject: [PATCH 4/7] Add configure script Generates makefile from template in pwd. Makes out of tree building simpler. Configures top_srcdir and top_builddir. Signed-off-by: Ola Jeppsson --- Makefile => Makefile.in | 18 ++++++++++++------ configure | 12 ++++++++++++ 2 files changed, 24 insertions(+), 6 deletions(-) rename Makefile => Makefile.in (57%) create mode 100755 configure diff --git a/Makefile b/Makefile.in similarity index 57% rename from Makefile rename to Makefile.in index b5102ce..6082828 100644 --- a/Makefile +++ b/Makefile.in @@ -1,6 +1,6 @@ have_vivado := $(shell which vivado 1>/dev/null 2>/dev/null && echo yes) -top_srcdir := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) -top_builddir := $(shell pwd) +top_srcdir := @top_srcdir@ +top_builddir := @top_builddir@ export @@ -16,12 +16,18 @@ builddeps: all: builddeps parallella-z7020 +# TODO parallella-z7020: builddeps - make -C targets/parallella-z7020/Makefile -# vivado -mode batch -source targets/parallella-z7020/system_project.tcl + vivado -mode batch -source $(top_srcdir)/projects/parallella-z7020/system_project.tcl -test: +# Temporary +package_axi_elink: builddeps vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/package_axi_elink.tcl +# Temporary +elink: builddeps + vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/run.tcl + clean: - find . \( -name vivado*.log -or -name vivado*.jou \) -delete + find . \( -name "vivado*.log" -or -name "vivado*.jou" \) -delete + diff --git a/configure b/configure new file mode 100755 index 0000000..e6f9f2f --- /dev/null +++ b/configure @@ -0,0 +1,12 @@ +#!/bin/bash + +if ! which vivado 1>/dev/null; then + echo ERROR: Vivado not in PATH + echo 'Try "source /opt/Xilinx/Vivado/201X.X/settings.sh"' + exit 1 +fi + +top_srcdir=$(dirname $(readlink -f "$0")) +top_builddir=$(pwd) +sed "s|@top_srcdir@|${top_srcdir}|g;s|@top_builddir@|${top_builddir}|g" \ + < $top_srcdir/Makefile.in > $top_builddir/Makefile From 5e16c906f747d1f8b6aa6a31ee8a9ef6daeb803b Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 23:32:28 +0200 Subject: [PATCH 5/7] Update README Add (work-in-progress) build instructions. Signed-off-by: Ola Jeppsson --- README.md | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index ccfbdc2..f959d04 100644 --- a/README.md +++ b/README.md @@ -2,4 +2,15 @@ # OH! Open Hardware (Pure and Simple) -(work in progress...) \ No newline at end of file +(work in progress...) + + +## Building +``` +git clone https://github.com/parallella/oh.git +cd oh +mkdir build +cd build +../configure +make elink +``` From 4df38ca35e531d8088e42b25392ec9d379f005fb Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 23:51:19 +0200 Subject: [PATCH 6/7] elink: Update scripts Use paths relative top top_srcdir (so scripts can be run from any directory). Add missing files elink_example was renamed to axi_elink? Fails at placement. Signed-off-by: Ola Jeppsson --- elink/scripts/xilinx/read_constraints.tcl | 11 ++- elink/scripts/xilinx/read_ip.tcl | 5 +- elink/scripts/xilinx/read_verilog.tcl | 86 ++++++++++++----------- elink/scripts/xilinx/run.tcl | 20 ++---- 4 files changed, 64 insertions(+), 58 deletions(-) diff --git a/elink/scripts/xilinx/read_constraints.tcl b/elink/scripts/xilinx/read_constraints.tcl index b1dcd98..a151a97 100644 --- a/elink/scripts/xilinx/read_constraints.tcl +++ b/elink/scripts/xilinx/read_constraints.tcl @@ -1,5 +1,10 @@ -set SRC /home/aolofsson/Work_all/oh -read_xdc $SRC/elink/syn/xilinx/elink_pins.xdc -read_xdc $SRC/elink/syn/xilinx/elink_timing.xdc +set pwd [file dirname [info script]] +source $pwd/../../../include/oh.tcl + +read_xdc $pwd/elink_pins.xdc +read_xdc $pwd/elink_timing.xdc + +# Do we need this? +#read_xdc $pwd/elink_clocks.xdc diff --git a/elink/scripts/xilinx/read_ip.tcl b/elink/scripts/xilinx/read_ip.tcl index a631e55..00c40d2 100644 --- a/elink/scripts/xilinx/read_ip.tcl +++ b/elink/scripts/xilinx/read_ip.tcl @@ -1,3 +1,6 @@ -read_ip ../../../xilibs/ip/fifo_async_104x16.xci +set pwd [file dirname [info script]] +source $pwd/../../../include/oh.tcl +read_ip $top_srcdir/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci +read_ip $top_srcdir/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci diff --git a/elink/scripts/xilinx/read_verilog.tcl b/elink/scripts/xilinx/read_verilog.tcl index 4effcf6..e60ac7e 100644 --- a/elink/scripts/xilinx/read_verilog.tcl +++ b/elink/scripts/xilinx/read_verilog.tcl @@ -1,54 +1,58 @@ -set SRC /home/aolofsson/Work_all/oh +set pwd [file dirname [info script]] +source $pwd/../../../include/oh.tcl #ONLY FOR REFERENCE EXAMPLE -read_verilog $SRC/elink/hdl/axi_elink.v +read_verilog $top_srcdir/elink/hdl/axi_elink.v #ELINK -read_verilog $SRC/elink/hdl/elink_constants.v -read_verilog $SRC/elink/hdl/elink_regmap.v -read_verilog $SRC/elink/hdl/elink.v -read_verilog $SRC/elink/hdl/eclocks.v -read_verilog $SRC/elink/hdl/ereset.v -read_verilog $SRC/elink/hdl/ecfg_elink.v -read_verilog $SRC/elink/hdl/ecfg_if.v -read_verilog $SRC/elink/hdl/erx.v -read_verilog $SRC/elink/hdl/erx_core.v -read_verilog $SRC/elink/hdl/erx_fifo.v -read_verilog $SRC/elink/hdl/erx_cfg.v -read_verilog $SRC/elink/hdl/erx_arbiter.v -read_verilog $SRC/elink/hdl/erx_protocol.v -read_verilog $SRC/elink/hdl/erx_remap.v -read_verilog $SRC/elink/hdl/erx_io.v -read_verilog $SRC/elink/hdl/etx.v -read_verilog $SRC/elink/hdl/etx_core.v -read_verilog $SRC/elink/hdl/etx_fifo.v -read_verilog $SRC/elink/hdl/etx_cfg.v -read_verilog $SRC/elink/hdl/etx_arbiter.v -read_verilog $SRC/elink/hdl/etx_protocol.v -read_verilog $SRC/elink/hdl/etx_remap.v -read_verilog $SRC/elink/hdl/etx_io.v +read_verilog $top_srcdir/elink/hdl/elink_constants.v +read_verilog $top_srcdir/elink/hdl/elink_regmap.v +read_verilog $top_srcdir/elink/hdl/elink.v +read_verilog $top_srcdir/elink/hdl/eclocks.v +read_verilog $top_srcdir/elink/hdl/ereset.v +read_verilog $top_srcdir/elink/hdl/ecfg_elink.v +read_verilog $top_srcdir/elink/hdl/ecfg_if.v +read_verilog $top_srcdir/elink/hdl/erx.v +read_verilog $top_srcdir/elink/hdl/erx_core.v +read_verilog $top_srcdir/elink/hdl/erx_fifo.v +read_verilog $top_srcdir/elink/hdl/erx_cfg.v +read_verilog $top_srcdir/elink/hdl/erx_arbiter.v +read_verilog $top_srcdir/elink/hdl/erx_protocol.v +read_verilog $top_srcdir/elink/hdl/erx_remap.v +read_verilog $top_srcdir/elink/hdl/erx_io.v +read_verilog $top_srcdir/elink/hdl/etx.v +read_verilog $top_srcdir/elink/hdl/etx_core.v +read_verilog $top_srcdir/elink/hdl/etx_fifo.v +read_verilog $top_srcdir/elink/hdl/etx_cfg.v +read_verilog $top_srcdir/elink/hdl/etx_arbiter.v +read_verilog $top_srcdir/elink/hdl/etx_protocol.v +read_verilog $top_srcdir/elink/hdl/etx_remap.v +read_verilog $top_srcdir/elink/hdl/etx_io.v +read_verilog $top_srcdir/elink/hdl/esaxi.v +read_verilog $top_srcdir/elink/hdl/emaxi.v #COMMON -read_verilog $SRC/common/hdl/toggle2pulse.v -read_verilog $SRC/common/hdl/synchronizer.v -read_verilog $SRC/common/hdl/pulse_stretcher.v -read_verilog $SRC/common/hdl/clock_divider.v -read_verilog $SRC/common/hdl/arbiter_priority.v +read_verilog $top_srcdir/common/hdl/toggle2pulse.v +read_verilog $top_srcdir/common/hdl/synchronizer.v +read_verilog $top_srcdir/common/hdl/pulse_stretcher.v +read_verilog $top_srcdir/common/hdl/clock_divider.v +read_verilog $top_srcdir/common/hdl/arbiter_priority.v #EMESH -read_verilog $SRC/emesh/hdl/emesh2packet.v -read_verilog $SRC/emesh/hdl/packet2emesh.v +read_verilog $top_srcdir/emesh/hdl/emesh2packet.v +read_verilog $top_srcdir/emesh/hdl/packet2emesh.v #MEMORY/FIFO -read_verilog $SRC/memory/hdl/fifo_async.v -read_verilog $SRC/memory/hdl/fifo_cdc.v -read_verilog $SRC/memory/hdl/memory_dp.v -read_verilog $SRC/memory/hdl/memory_sp.v -read_verilog $SRC/memory/hdl/fifo_full_block.v -read_verilog $SRC/memory/hdl/fifo_empty_block.v +read_verilog $top_srcdir/memory/hdl/fifo_async.v +read_verilog $top_srcdir/memory/hdl/fifo_sync.v +read_verilog $top_srcdir/memory/hdl/fifo_cdc.v +read_verilog $top_srcdir/memory/hdl/memory_dp.v +read_verilog $top_srcdir/memory/hdl/memory_sp.v +read_verilog $top_srcdir/memory/hdl/fifo_full_block.v +read_verilog $top_srcdir/memory/hdl/fifo_empty_block.v #MMU -read_verilog $SRC/emmu/hdl/emmu.v -read_verilog $SRC/emailbox/hdl/emailbox.v -read_verilog $SRC/edma/hdl/edma.v +read_verilog $top_srcdir/emmu/hdl/emmu.v +read_verilog $top_srcdir/emailbox/hdl/emailbox.v +read_verilog $top_srcdir/edma/hdl/edma.v diff --git a/elink/scripts/xilinx/run.tcl b/elink/scripts/xilinx/run.tcl index 167a254..76095bc 100644 --- a/elink/scripts/xilinx/run.tcl +++ b/elink/scripts/xilinx/run.tcl @@ -1,17 +1,20 @@ +set pwd [file dirname [info script]] +source $pwd/../../../include/oh.tcl + ########################################################### #STEP0: Define variables set OUTDIR ./tmp set PART xc7z010clg400-1 -set TOP elink_example +set TOP axi_elink file mkdir $OUTDIR ########################################################### #STEP1: Read sources, constraints, IP files create_project -in_memory -part $PART -force my_project -source read_verilog.tcl -source read_constraints.tcl -source read_ip.tcl +source $pwd/read_verilog.tcl +source $pwd/read_constraints.tcl +source $pwd/read_ip.tcl ########################################################### #STEP2: SYNTHESIS @@ -79,12 +82,3 @@ write_verilog -force $OUTDIR/$TOP.v write_xdc -no_fixed_only -force $OUTDIR/$TOP.xdc write_bitstream -force $OUTDIR/$TOP.bit - - - - - - - - - From 4f48bdca032edb488e6246d8613d92519219ce2f Mon Sep 17 00:00:00 2001 From: Ola Jeppsson Date: Sun, 5 Jul 2015 23:51:46 +0200 Subject: [PATCH 7/7] projects/axi_elink: Add missing fifo Add fifo_async_104x32.xci Signed-off-by: Ola Jeppsson --- projects/axi_elink/axi_elink_oh.tcl | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/projects/axi_elink/axi_elink_oh.tcl b/projects/axi_elink/axi_elink_oh.tcl index e790c26..04f756a 100755 --- a/projects/axi_elink/axi_elink_oh.tcl +++ b/projects/axi_elink/axi_elink_oh.tcl @@ -32,7 +32,8 @@ update_ip_catalog -rebuild # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - "[file normalize "$oh_path/xilibs/ip/fifo_async_104x16.xci"]"\ + "[file normalize "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"]"\ + "[file normalize "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"]"\ "[file normalize "$oh_path/memory/hdl/fifo_async.v"]"\ "[file normalize "$oh_path/memory/hdl/memory_dp.v"]"\ "[file normalize "$oh_path/emesh/hdl/packet2emesh.v"]"\ @@ -76,7 +77,7 @@ set files [list \ add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$oh_path/xilibs/ip/fifo_async_104x16.xci" +set file "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] if { ![get_property "is_locked" $file_obj] } { @@ -84,6 +85,17 @@ if { ![get_property "is_locked" $file_obj] } { } set_property "used_in_implementation" "0" $file_obj +# Set 'sources_1' fileset file properties for remote files +set file "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +if { ![get_property "is_locked" $file_obj] } { + set_property "synth_checkpoint_mode" "Singular" $file_obj +} +set_property "used_in_implementation" "0" $file_obj + + + set file "$oh_path/memory/hdl/fifo_async.v" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]