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Fixed issue with DC verilog parser

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-Apparentely "|=" is not allowed??
This commit is contained in:
Andreas.Olofsson 2020-08-08 22:22:52 -04:00
parent d7769070fc
commit 0d61520268
1 changed files with 1 additions and 1 deletions
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common/hdl/oh_mux.v
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@ -21,7 +21,7 @@ module oh_mux #( parameter DW = 1, // width of data inputs
begin
out[DW-1:0] = 'b0;
for(i=0;i<N;i=i+1)
out[DW-1:0] |= {(DW){sel[i]}} & in[((i+1)*DW-1)-:DW];
out[DW-1:0] = out[DW-1:0] | {(DW){sel[i]}} & in[((i+1)*DW-1)-:DW];
end
endmodule // oh_mux