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Fixed issue with DC verilog parser
-Apparentely "|=" is not allowed??
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@ -21,7 +21,7 @@ module oh_mux #( parameter DW = 1, // width of data inputs
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begin
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begin
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out[DW-1:0] = 'b0;
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out[DW-1:0] = 'b0;
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for(i=0;i<N;i=i+1)
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for(i=0;i<N;i=i+1)
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out[DW-1:0] |= {(DW){sel[i]}} & in[((i+1)*DW-1)-:DW];
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out[DW-1:0] = out[DW-1:0] | {(DW){sel[i]}} & in[((i+1)*DW-1)-:DW];
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end
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end
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endmodule // oh_mux
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endmodule // oh_mux
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