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Added tag and group for read response
-Still not sure about this..
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@ -19,9 +19,10 @@ module erx_disty (/*AUTOARG*/
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);
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parameter [11:0] C_READ_TAG_ADDR = 12'h810;
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parameter [11:0] C_READ_TAG_ADDR = 12'h810;
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parameter AW = 32;
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parameter AW = 32;
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parameter DW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter PW = 104;
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parameter ID = 12'h800; //link id
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// RX clock
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// RX clock
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input clk;
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input clk;
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@ -64,6 +65,7 @@ module erx_disty (/*AUTOARG*/
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wire [31:0] emmu_srcaddr;
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wire [31:0] emmu_srcaddr;
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wire [31:0] emmu_data;
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wire [31:0] emmu_data;
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wire emmu_read;
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wire emmu_read;
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wire readtag_match;
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//regs
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//regs
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reg rxrd_fifo_access;
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reg rxrd_fifo_access;
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@ -104,7 +106,7 @@ module erx_disty (/*AUTOARG*/
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end
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end
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//Write and read response from emmu
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//Write and read response from emmu
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assign readtag_match = (emmu_dstaddr[31:20] == ID) & (emmu_dstaddr[19:16]==`EGROUP_READTAG) ;
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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if(reset)
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if(reset)
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@ -115,8 +117,8 @@ module erx_disty (/*AUTOARG*/
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else if(emmu_access)
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else if(emmu_access)
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begin
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begin
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rxwr_fifo_packet[PW-1:0] <= emmu_packet[PW-1:0];
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rxwr_fifo_packet[PW-1:0] <= emmu_packet[PW-1:0];
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rxrr_fifo_access <= emmu_write & (emmu_dstaddr[31:20] == C_READ_TAG_ADDR);
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rxrr_fifo_access <= emmu_write & readtag_match; //read response match
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rxwr_fifo_access <= emmu_write & (emmu_dstaddr[31:20] != C_READ_TAG_ADDR);
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rxwr_fifo_access <= emmu_write & ~(emmu_dstaddr[31:20] == ID);//pass through
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end
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end
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else
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else
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begin
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begin
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@ -129,7 +131,7 @@ module erx_disty (/*AUTOARG*/
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//wait signals
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//wait signals
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assign rx_rd_wait = rxrd_fifo_wait;
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assign rx_rd_wait = rxrd_fifo_wait;
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assign rx_wr_wait = rxwr_fifo_wait | rxrr_fifo_wait;
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assign rx_wr_wait = rxwr_fifo_wait | rxrr_fifo_wait;
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assign edma_wait = rxrd_fifo_wait | emmu_read;
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assign edma_wait = rxrd_fifo_wait | emmu_read;
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endmodule // erx_disty
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endmodule // erx_disty
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// Local Variables:
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// Local Variables:
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