diff --git a/elink/dv/lint.sh b/elink/dv/lint.sh
new file mode 100755
index 0000000..d3b0540
--- /dev/null
+++ b/elink/dv/lint.sh
@@ -0,0 +1,2 @@
+#!/bin/bash
+verilator --lint-only -f ../../common/dv/libs.cmd $1 -DTARGET_VERILATOR=1 -DTARGET_XILINX=1;
diff --git a/emesh/dv/ememory.v b/emesh/dv/ememory.v
index ffedb29..58979d0 100644
--- a/emesh/dv/ememory.v
+++ b/emesh/dv/ememory.v
@@ -183,13 +183,13 @@ module ememory(/*AUTOARG*/
    generate
       if(WAIT)
 	begin	   
-	   reg [7:0] wait_counter;  
+	   reg [8:0] wait_counter;  
 	   always @ (posedge clk or negedge nreset)
 	     if(!nreset)
-	       wait_counter[7:0] <= 'b0;   
+	       wait_counter[8:0] <= 'b0;   
 	     else
-	       wait_counter[7:0] <= wait_counter+1'b1;         
-	   assign wait_random      = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0;
+	       wait_counter[8:0] <= wait_counter+1'b1;         
+	   assign wait_random      = (|wait_counter[5:0]);//(|wait_counter[3:0]);//1'b0;
 	end
       else
 	begin
diff --git a/xilibs/hdl/PLLE2_ADV.v b/xilibs/hdl/PLLE2_ADV.v
index 9219550..cdc2292 100644
--- a/xilibs/hdl/PLLE2_ADV.v
+++ b/xilibs/hdl/PLLE2_ADV.v
@@ -144,11 +144,17 @@ module PLLE2_ADV #(
 
    reg [5:0] CLKOUT_DIV_LOCK;   
 
+`ifdef TARGET_VERILATOR
+   initial
+     begin
+	$display("ERROR: PLL divider not implemented");	
+     end
+`else   
    always @ (posedge (CLKIN1 & vco_clk) or negedge (CLKIN1&~vco_clk))
      begin
 	CLKOUT_DIV_LOCK[5:0] <= CLKOUT_DIV[5:0];	
      end
-
+`endif
    
    //##############
    //#SUB PHASE DELAY
diff --git a/xilibs/ip/fifo_generator_vlog_beh.v b/xilibs/ip/fifo_generator_vlog_beh.v
index c027839..f158405 100644
--- a/xilibs/ip/fifo_generator_vlog_beh.v
+++ b/xilibs/ip/fifo_generator_vlog_beh.v
@@ -1,3 +1,9 @@
+
+/*verilator lint_off IMPLICIT*/
+/*verilator lint_off WIDTH*/
+/*verilator lint_off LITENDIAN*/
+/* verilator lint_off COMBDLY*/
+
 /*
  *******************************************************************************
  *