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Merge pull request #78 from olajep/spi-fpga-project

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SPI fpga project
This commit is contained in:
Andreas Olofsson 2016-05-04 14:24:55 -04:00
commit 10cad20205
13 changed files with 788 additions and 0 deletions
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3
src/spi/fpga/axi_spi_timing.xdc Normal file
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# SPI slave clock
create_clock -name spi_s_sclk -period 10 [get_ports spi_s_sclk]

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src/spi/fpga/bit2bin.bif Normal file
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the_ROM_image:
{
[bootloader]dummy.elf
./system.runs/impl_1/system_wrapper.bit
}

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src/spi/fpga/build.sh Executable file
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#!/bin/bash
#clean up
rm system_wrapper.bit.bin bit2bin.bin
#package IP
vivado -mode batch -source package.tcl
#create bit stream
vivado -mode batch -source run.tcl
#xilinx stuff...
bootgen -image bit2bin.bif -split bin
cp system_wrapper.bit.bin parallella.bit.bin

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src/spi/fpga/clean.sh Executable file
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#!/bin/sh
rm -rf component.xml
rm -rf parallella.bit.bin
rm -rf parallella_spi.cache
rm -rf parallella_spi.hw
rm -rf parallella_spi.sim
rm -rf parallella_spi.xpr
rm -rf parallella_spi.zip
rm -rf reports
rm -rf results
rm -rf src
rm -rf system.cache
rm -rf system.hw
rm -rf system.runs
rm -rf system.sim
rm -rf system.srcs
rm -rf system_wrapper.bit.bin
rm -rf system.xpr
rm -rf vivado*.jou
rm -rf vivado*.log
rm -rf xgui

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src/spi/fpga/dummy.elf Normal file
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src/spi/fpga/ip_params.tcl Normal file
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# NOTE: See UG1118 for more information
set design parallella_spi
set projdir ./
set root "../.."
set partname "xc7z020clg400-1"
set hdl_files [list \
$root/spi/hdl \
$root/common/hdl/ \
$root/emesh/hdl \
$root/emmu/hdl \
$root/axi/hdl \
$root/emailbox/hdl \
$root/edma/hdl \
$root/elink/hdl \
$root/parallella/hdl \
]
set ip_files []
set constraints_files []

3
src/spi/fpga/package.tcl Normal file
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#STEP1: DEFINE KEY PARAMETERS
source ./ip_params.tcl
source ../../common/fpga/create_ip.tcl

12
src/spi/fpga/run.tcl Normal file
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#STEP1: DEFINE KEY PARAMETERS
source ./run_params.tcl
#STEP2: CREATE PROJECT AND READ IN FILES
source ../../common/fpga/system_init.tcl
#STEP 3 (OPTIONAL): EDIT system.bd in VIVADO gui, then go to STEP 4.
##...
#STEP 4: SYNTEHSIZE AND CREATE BITSTRAM
source ../../common/fpga/system_build.tcl

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src/spi/fpga/run_params.tcl Normal file
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#Design name ("system" recommended)
set design system
#Project directory ("." recommended)
set projdir ./
#Device name
set partname "xc7z020clg400-1"
#Paths to all IP blocks to use in Vivado "system.bd"
set ip_repos [list "."]
#All source files
set hdl_files []
#All constraints files
set constraints_files [list \
../../parallella/fpga/parallella_io.xdc \
../../parallella/fpga/parallella_7020_io.xdc \
./axi_spi_timing.xdc \
]

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src/spi/fpga/system_bd.tcl Normal file
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################################################################
# This is a generated script based on design: system
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source system_script.tcl
# If you do not already have a project created,
# you can create a project using the following command:
# create_project project_1 myproj -part xc7z020clg400-1
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# CHANGE DESIGN NAME HERE
set design_name system
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
puts "INFO: Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
set gpio_n [ create_bd_port -dir IO -from 23 -to 0 gpio_n ]
set gpio_p [ create_bd_port -dir IO -from 23 -to 0 gpio_p ]
# Create instance: parallella_spi_0, and set properties
set parallella_spi_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:parallella_spi:1.0 parallella_spi_0 ]
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list CONFIG.PCW_CORE0_FIQ_INTR {0} \
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_I2C0_I2C0_IO {EMIO} CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_I2C0_RESET_ENABLE {0} CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.434} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.398} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.410} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.455} CONFIG.PCW_UIPARAM_DDR_CL {9} \
CONFIG.PCW_UIPARAM_DDR_CWL {9} CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {8192 MBits} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.315} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.391} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.374} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.271} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {32 Bits} CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {400.00} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} CONFIG.PCW_UIPARAM_DDR_T_FAW {50} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {40} CONFIG.PCW_UIPARAM_DDR_T_RC {60} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {9} CONFIG.PCW_UIPARAM_DDR_T_RP {9} \
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USB0_RESET_ENABLE {0} CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_USE_M_AXI_GP1 {1} \
CONFIG.PCW_USE_S_AXI_HP1 {1} ] $processing_system7_0
# Create instance: processing_system7_0_axi_periph, and set properties
set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ]
set_property -dict [ list CONFIG.NUM_MI {1} ] $processing_system7_0_axi_periph
# Create instance: sys_concat_intc, and set properties
set sys_concat_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc ]
set_property -dict [ list CONFIG.NUM_PORTS {16} ] $sys_concat_intc
# Create interface connections
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP1 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins parallella_spi_0/s_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]
# Create port connections
connect_bd_net -net parallella_spi_0_constant_zero [get_bd_pins sys_concat_intc/In0] [get_bd_pins sys_concat_intc/In1] [get_bd_pins sys_concat_intc/In2] [get_bd_pins sys_concat_intc/In3] [get_bd_pins sys_concat_intc/In4] [get_bd_pins sys_concat_intc/In5] [get_bd_pins sys_concat_intc/In6] [get_bd_pins sys_concat_intc/In7] [get_bd_pins sys_concat_intc/In8] [get_bd_pins sys_concat_intc/In10] [get_bd_pins sys_concat_intc/In11] [get_bd_pins sys_concat_intc/In12] [get_bd_pins sys_concat_intc/In13] [get_bd_pins sys_concat_intc/In14] [get_bd_pins sys_concat_intc/In15]
connect_bd_net -net parallella_spi_0_gpio_n [get_bd_ports gpio_n] [get_bd_pins parallella_spi_0/gpio_n]
connect_bd_net -net parallella_spi_0_gpio_p [get_bd_ports gpio_p] [get_bd_pins parallella_spi_0/gpio_p]
connect_bd_net -net parallella_spi_0_spi_irq [get_bd_pins parallella_spi_0/spi_irq] [get_bd_pins sys_concat_intc/In9]
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins processing_system7_0_axi_periph/ARESETN]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins parallella_spi_0/s_axi_aresetn] [get_bd_pins parallella_spi_0/sys_nreset] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins parallella_spi_0/sys_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
connect_bd_net -net sys_concat_intc_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins sys_concat_intc/dout]
# Create address segments
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs parallella_spi_0/s_axi/axi_lite] SEG_parallella_spi_0_axi_lite
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""

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src/spi/fpga/system_params.tcl Normal file
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# NOTE: See UG1118 for more information
#########################################
# VARIABLES
#########################################
set design axi_spi
set projdir ./
set root "../.."
set partname "xc7z020clg400-1"
set hdl_files [list \
$root/spi/hdl \
$root/common/hdl/ \
$root/emesh/hdl \
$root/emmu/hdl \
$root/axi/hdl \
$root/emailbox/hdl \
$root/edma/hdl \
$root/elink/hdl \
$root/parallella/hdl \
]
set ip_files []
set constraints_files [list \
../../parallella/fpga/parallella_io.xdc \
../../parallella/fpga/parallella_7020_io.xdc \
./axi_spi_timing.xdc \
]

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src/spi/hdl/axi_spi.v Normal file
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//#############################################################################
//# Purpose: AXI spi module #
//#############################################################################
//# Author: Ola Jeppsson #
//# SPDX-License-Identifier: MIT #
//#############################################################################
module axi_spi(/*AUTOARG*/
// Outputs
spi_s_miso, spi_m_ss, spi_m_sclk, spi_m_mosi, spi_irq,
s_axi_wready, s_axi_rvalid, s_axi_rresp, s_axi_rlast, s_axi_rid,
s_axi_rdata, s_axi_bvalid, s_axi_bresp, s_axi_bid, s_axi_awready,
s_axi_arready,
// Inputs
spi_s_ss, spi_s_sclk, spi_s_mosi, spi_m_miso, s_axi_wvalid,
s_axi_wstrb, s_axi_wlast, s_axi_wid, s_axi_wdata, s_axi_rready,
s_axi_bready, s_axi_awvalid, s_axi_awsize, s_axi_awqos,
s_axi_awprot, s_axi_awlock, s_axi_awlen, s_axi_awid, s_axi_awcache,
s_axi_awburst, s_axi_awaddr, s_axi_arvalid, s_axi_arsize,
s_axi_arqos, s_axi_arprot, s_axi_arlock, s_axi_arlen, s_axi_arid,
s_axi_aresetn, s_axi_arcache, s_axi_arburst, s_axi_araddr,
sys_nreset, sys_clk
);
//########################################################
// INTERFACE
//########################################################
parameter AW = 32; // address width
parameter PW = 2*AW+40; // packet width
parameter ID = 12'h810; // addr[31:20] id
parameter S_IDW = 12; // ID width for S_AXI
//clk, reset
input sys_nreset; // active low async reset
input sys_clk; // system clock for AXI
//############################
// HOST GENERATERD
//############################
//Slave Write
wire s_wr_access;
wire [PW-1:0] s_wr_packet;
wire s_wr_wait;
//Slave Read Request
wire s_rd_access;
wire [PW-1:0] s_rd_packet;
wire s_rd_wait;
//Slave Read Response
wire s_rr_access;
wire [PW-1:0] s_rr_packet;
wire s_rr_wait;
//##############################################################
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] s_axi_araddr; // To esaxi of esaxi.v
input [1:0] s_axi_arburst; // To esaxi of esaxi.v
input [3:0] s_axi_arcache; // To esaxi of esaxi.v
input s_axi_aresetn; // To esaxi of esaxi.v
input [S_IDW-1:0] s_axi_arid; // To esaxi of esaxi.v
input [7:0] s_axi_arlen; // To esaxi of esaxi.v
input s_axi_arlock; // To esaxi of esaxi.v
input [2:0] s_axi_arprot; // To esaxi of esaxi.v
input [3:0] s_axi_arqos; // To esaxi of esaxi.v
input [2:0] s_axi_arsize; // To esaxi of esaxi.v
input s_axi_arvalid; // To esaxi of esaxi.v
input [31:0] s_axi_awaddr; // To esaxi of esaxi.v
input [1:0] s_axi_awburst; // To esaxi of esaxi.v
input [3:0] s_axi_awcache; // To esaxi of esaxi.v
input [S_IDW-1:0] s_axi_awid; // To esaxi of esaxi.v
input [7:0] s_axi_awlen; // To esaxi of esaxi.v
input s_axi_awlock; // To esaxi of esaxi.v
input [2:0] s_axi_awprot; // To esaxi of esaxi.v
input [3:0] s_axi_awqos; // To esaxi of esaxi.v
input [2:0] s_axi_awsize; // To esaxi of esaxi.v
input s_axi_awvalid; // To esaxi of esaxi.v
input s_axi_bready; // To esaxi of esaxi.v
input s_axi_rready; // To esaxi of esaxi.v
input [31:0] s_axi_wdata; // To esaxi of esaxi.v
input [S_IDW-1:0] s_axi_wid; // To esaxi of esaxi.v
input s_axi_wlast; // To esaxi of esaxi.v
input [3:0] s_axi_wstrb; // To esaxi of esaxi.v
input s_axi_wvalid; // To esaxi of esaxi.v
input spi_m_miso; // To spi of spi.v
input spi_s_mosi; // To spi of spi.v
input spi_s_sclk; // To spi of spi.v
input spi_s_ss; // To spi of spi.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output s_axi_arready; // From esaxi of esaxi.v
output s_axi_awready; // From esaxi of esaxi.v
output [S_IDW-1:0] s_axi_bid; // From esaxi of esaxi.v
output [1:0] s_axi_bresp; // From esaxi of esaxi.v
output s_axi_bvalid; // From esaxi of esaxi.v
output [31:0] s_axi_rdata; // From esaxi of esaxi.v
output [S_IDW-1:0] s_axi_rid; // From esaxi of esaxi.v
output s_axi_rlast; // From esaxi of esaxi.v
output [1:0] s_axi_rresp; // From esaxi of esaxi.v
output s_axi_rvalid; // From esaxi of esaxi.v
output s_axi_wready; // From esaxi of esaxi.v
output spi_irq; // From spi of spi.v
output spi_m_mosi; // From spi of spi.v
output spi_m_sclk; // From spi of spi.v
output spi_m_ss; // From spi of spi.v
output spi_s_miso; // From spi of spi.v
// End of automatics
/*AUTOWIRE*/
/*AUTOREG*/
wire spi_wait_out;
wire spi_access_out;
wire [PW-1:0] spi_packet_out;
wire spi_access_in;
wire [PW-1:0] spi_packet_in;
wire spi_wait_in;
/* spi AUTO_TEMPLATE (.\([sm]_.*\) (spi_\1[]),); */
spi #(.AW(AW))
spi (
//Outputs
.hw_en (1'b1),
.wait_out (spi_wait_out),
.access_out (spi_access_out),
.packet_out (spi_packet_out[PW-1:0]),
//Inputs
.nreset (sys_nreset),
.clk (sys_clk),
.access_in (spi_access_in),
.packet_in (spi_packet_in[PW-1:0]),
.wait_in (spi_wait_in),
/*AUTOINST*/
// Outputs
.spi_irq (spi_irq),
.m_sclk (spi_m_sclk), // Templated
.m_mosi (spi_m_mosi), // Templated
.m_ss (spi_m_ss), // Templated
.s_miso (spi_s_miso), // Templated
// Inputs
.m_miso (spi_m_miso), // Templated
.s_sclk (spi_s_sclk), // Templated
.s_mosi (spi_s_mosi), // Templated
.s_ss (spi_s_ss)); // Templated
//########################################################
//AXI SLAVE
//########################################################
emesh_mux #(.N(2),.AW(AW))
mux2(// Outputs
.wait_out ({s_rd_wait, s_wr_wait}),
.access_out (spi_access_in),
.packet_out (spi_packet_in[PW-1:0]),
// Inputs
.access_in ({s_rd_access, s_wr_access}),
.packet_in ({s_rd_packet[PW-1:0], s_wr_packet[PW-1:0]}),
.wait_in (s_rr_wait)
);
esaxi #(.S_IDW(S_IDW))
esaxi (.s_axi_aclk (sys_clk),
.wr_access (s_wr_access),
.wr_packet (s_wr_packet[PW-1:0]),
.rr_wait (s_rr_wait),
.rd_wait (s_rd_wait),
.rr_access (spi_access_out),
.rr_packet (spi_packet_out[PW-1:0]),
.wr_wait (s_wr_wait),
.rd_access (s_rd_access),
.rd_packet (s_rd_packet[PW-1:0]),
/*AUTOINST*/
// Outputs
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
endmodule // axi_spi
// Local Variables:
// verilog-library-directories:("." "../../axi/hdl" "../../common/hdl" "../../emesh/hdl")
// End:

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src/spi/hdl/parallella_spi.v Normal file
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//#############################################################################
//# Purpose: Parallella SPI top #
//#############################################################################
//# Author: Ola Jeppsson #
//# SPDX-License-Identifier: MIT #
//#############################################################################
module parallella_spi(/*AUTOARG*/
// Outputs
spi_s_miso, spi_m_ss, spi_m_sclk, spi_m_mosi, spi_irq,
s_axi_wready, s_axi_rvalid, s_axi_rresp, s_axi_rlast, s_axi_rid,
s_axi_rdata, s_axi_bvalid, s_axi_bresp, s_axi_bid, s_axi_awready,
s_axi_arready,
// Inouts
gpio_n, gpio_p,
// Inputs
s_axi_wvalid, s_axi_wstrb, s_axi_wlast, s_axi_wid, s_axi_wdata,
s_axi_rready, s_axi_bready, s_axi_awvalid, s_axi_awsize,
s_axi_awqos, s_axi_awprot, s_axi_awlock, s_axi_awlen, s_axi_awid,
s_axi_awcache, s_axi_awburst, s_axi_awaddr, s_axi_arvalid,
s_axi_arsize, s_axi_arqos, s_axi_arprot, s_axi_arlock, s_axi_arlen,
s_axi_arid, s_axi_aresetn, s_axi_arcache, s_axi_arburst,
s_axi_araddr, constant_zero, constant_one, sys_nreset, sys_clk
);
//########################################################
// INTERFACE
//########################################################
parameter AW = 32; // address width
parameter DW = 32;
parameter PW = 2*AW+40; // packet width
parameter ID = 12'h820; // addr[31:20] id
parameter S_IDW = 12; // ID width for S_AXI
parameter NGPIO = 24; // number of gpio pins
// constants
input constant_zero; // Always 0
input constant_one; // Always 1
//clk, reset
input sys_nreset; // active low async reset
input sys_clk; // system clock for AXI
// gpio pins
inout [NGPIO-1:0] gpio_n; // physical spi pins
inout [NGPIO-1:0] gpio_p; // physical spi pins
wire [NGPIO-1:0] gpio_in; // out gpio pins
wire [NGPIO-1:0] gpio_out; // in gpio pins
wire [NGPIO-1:0] gpio_dir; // gpio pin direction
// spi
wire spi_s_miso;
wire spi_m_ss;
wire spi_m_sclk;
wire spi_m_mosi;
wire spi_s_ss;
wire spi_s_sclk;
wire spi_s_mosi;
wire spi_m_miso;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] s_axi_araddr; // To axi_spi of axi_spi.v
input [1:0] s_axi_arburst; // To axi_spi of axi_spi.v
input [3:0] s_axi_arcache; // To axi_spi of axi_spi.v
input s_axi_aresetn; // To axi_spi of axi_spi.v
input [S_IDW-1:0] s_axi_arid; // To axi_spi of axi_spi.v
input [7:0] s_axi_arlen; // To axi_spi of axi_spi.v
input s_axi_arlock; // To axi_spi of axi_spi.v
input [2:0] s_axi_arprot; // To axi_spi of axi_spi.v
input [3:0] s_axi_arqos; // To axi_spi of axi_spi.v
input [2:0] s_axi_arsize; // To axi_spi of axi_spi.v
input s_axi_arvalid; // To axi_spi of axi_spi.v
input [31:0] s_axi_awaddr; // To axi_spi of axi_spi.v
input [1:0] s_axi_awburst; // To axi_spi of axi_spi.v
input [3:0] s_axi_awcache; // To axi_spi of axi_spi.v
input [S_IDW-1:0] s_axi_awid; // To axi_spi of axi_spi.v
input [7:0] s_axi_awlen; // To axi_spi of axi_spi.v
input s_axi_awlock; // To axi_spi of axi_spi.v
input [2:0] s_axi_awprot; // To axi_spi of axi_spi.v
input [3:0] s_axi_awqos; // To axi_spi of axi_spi.v
input [2:0] s_axi_awsize; // To axi_spi of axi_spi.v
input s_axi_awvalid; // To axi_spi of axi_spi.v
input s_axi_bready; // To axi_spi of axi_spi.v
input s_axi_rready; // To axi_spi of axi_spi.v
input [31:0] s_axi_wdata; // To axi_spi of axi_spi.v
input [S_IDW-1:0] s_axi_wid; // To axi_spi of axi_spi.v
input s_axi_wlast; // To axi_spi of axi_spi.v
input [3:0] s_axi_wstrb; // To axi_spi of axi_spi.v
input s_axi_wvalid; // To axi_spi of axi_spi.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output s_axi_arready; // From axi_spi of axi_spi.v
output s_axi_awready; // From axi_spi of axi_spi.v
output [S_IDW-1:0] s_axi_bid; // From axi_spi of axi_spi.v
output [1:0] s_axi_bresp; // From axi_spi of axi_spi.v
output s_axi_bvalid; // From axi_spi of axi_spi.v
output [31:0] s_axi_rdata; // From axi_spi of axi_spi.v
output [S_IDW-1:0] s_axi_rid; // From axi_spi of axi_spi.v
output s_axi_rlast; // From axi_spi of axi_spi.v
output [1:0] s_axi_rresp; // From axi_spi of axi_spi.v
output s_axi_rvalid; // From axi_spi of axi_spi.v
output s_axi_wready; // From axi_spi of axi_spi.v
output spi_irq; // From axi_spi of axi_spi.v
output spi_m_mosi; // From axi_spi of axi_spi.v
output spi_m_sclk; // From axi_spi of axi_spi.v
output spi_m_ss; // From axi_spi of axi_spi.v
output spi_s_miso; // From axi_spi of axi_spi.v
// End of automatics
/*AUTOWIRE*/
/*AUTOREG*/
assign spi_s_ss = gpio_in[10];
assign spi_s_miso = gpio_out[9];
assign spi_s_mosi = gpio_in[8];
assign spi_s_sclk = gpio_in[7]; /* Must map to a MRCC/SRCC pin */
assign spi_m_ss = gpio_out[6];
assign spi_m_miso = gpio_in[5];
assign spi_m_mosi = gpio_out[4];
assign spi_m_sclk = gpio_out[3];
/* NOTE: 0 = in, 1 = out */
assign gpio_dir[NGPIO-1:0] = {{(NGPIO-8){1'b0}}, 8'b01001011};
assign constant_zero = 1'b0;
assign constant_one = 1'b1;
pgpio #(.NGPIO(NGPIO),.NPS(NGPIO))
pgpio (.ps_gpio_i (gpio_in[NGPIO-1:0]),
.ps_gpio_o (gpio_out[NGPIO-1:0]),
.ps_gpio_t (~gpio_dir[NGPIO-1:0]),
/*AUTOINST*/
// Inouts
.gpio_p (gpio_p[NGPIO-1:0]),
.gpio_n (gpio_n[NGPIO-1:0]));
axi_spi #(.S_IDW(S_IDW),.AW(AW),.ID(ID))
axi_spi (// Outputs
.spi_irq (spi_irq),
.spi_m_mosi (spi_m_mosi),
.spi_m_sclk (spi_m_sclk),
.spi_m_ss (spi_m_ss),
.spi_s_miso (spi_s_miso),
// Inputs
.spi_m_miso (spi_m_miso),
.spi_s_mosi (spi_s_mosi),
.spi_s_sclk (spi_s_sclk),
.spi_s_ss (spi_s_ss),
/*AUTOINST*/
// Outputs
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.sys_nreset (sys_nreset),
.sys_clk (sys_clk),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arlock (s_axi_arlock),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awlock (s_axi_awlock),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
endmodule // parallella_spi
// Local Variables:
// verilog-library-directories:("." "../../axi/hdl" "../../common/hdl" "../../emesh/hdl" "../../parallella/hdl")
// End: