From 1346c0280363092d6a328d96678632758bf34436 Mon Sep 17 00:00:00 2001
From: aolofsson <andreas@adapteva.com>
Date: Mon, 15 Dec 2014 15:25:09 -0500
Subject: [PATCH] Verilator inspired bug fixes -address width in elink -bus
 widths in ecfg -command file more generic

---
 elink/dv/elink.cmd |  4 +++-
 elink/hdl/ecfg.v   | 18 +++++++++---------
 elink/hdl/elink.v  |  6 +++---
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/elink/dv/elink.cmd b/elink/dv/elink.cmd
index e3fb706..5d52f25 100644
--- a/elink/dv/elink.cmd
+++ b/elink/dv/elink.cmd
@@ -1,3 +1,4 @@
+=y .
 -y ../hdl
 -y ../../common/hdl
 -y ../../axi/hdl
@@ -8,4 +9,5 @@
 -y ../../stubs/hdl
 -y ../../erx/hdl
 -y ../../etx/hdl
-dv_elink.v
+
+
diff --git a/elink/hdl/ecfg.v b/elink/hdl/ecfg.v
index 8603c8d..6a69d1d 100644
--- a/elink/hdl/ecfg.v
+++ b/elink/hdl/ecfg.v
@@ -112,7 +112,7 @@ module ecfg (/*AUTOARG*/
    ecfg_rx_gpio_mode, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg,
    ecfg_coreid, ecfg_dataout,
    // Inputs
-   mi_clk, mi_en, mi_we, mi_addr, mi_din, hw_reset, ecfg_datain,
+   hw_reset, mi_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_datain,
    ecfg_debug_signals
    );
    //Register file parameters
@@ -189,8 +189,8 @@ module ecfg (/*AUTOARG*/
    reg [7:0] 	ecfg_cfgclk_reg;
    reg [11:0] 	ecfg_coreid_reg;
    reg          ecfg_reset_reg;
-   reg [11:0] 	ecfg_datain_reg;
-   reg [11:0] 	ecfg_dataout_reg;
+   reg [10:0] 	ecfg_datain_reg;
+   reg [10:0] 	ecfg_dataout_reg;
    reg [31:0] 	mi_dout;
    
    //wires
@@ -213,6 +213,7 @@ module ecfg (/*AUTOARG*/
    wire 	ecfg_dataout_write;
    wire 	ecfg_rx_monitor_mode;
    wire 	ecfg_reset_write;
+   wire         ecfg_version_match;
    
    /*****************************/
    /*ADDRESS DECODE LOGIC       */
@@ -278,7 +279,6 @@ module ecfg (/*AUTOARG*/
    assign ecfg_rx_enable        = ecfg_cfgrx_reg[0];
    assign ecfg_rx_mmu_mode      = ecfg_cfgrx_reg[1];   
    assign ecfg_rx_gpio_mode     = ecfg_cfgrx_reg[3:2]==2'b01;
-   assign ecfg_rx_loopback_mode = ecfg_cfgrx_reg[3:2]==2'b10;
    assign ecfg_rx_monitor_mode  = ecfg_cfgrx_reg[4];
 
    //###########################
@@ -309,16 +309,16 @@ module ecfg (/*AUTOARG*/
    //# ESYSDATAIN
    //###########################
    always @ (posedge mi_clk)
-     ecfg_datain_reg <= ecfg_datain;
+     ecfg_datain_reg[10:0] <= ecfg_datain[10:0];
    
    //###########################
    //# ESYSDATAOUT
    //###########################
    always @ (posedge mi_clk)
      if(hw_reset)
-       ecfg_dataout_reg <= 'd0;   
+       ecfg_dataout_reg[10:0] <= 11'd0;   
      else if (ecfg_dataout_write)
-       ecfg_dataout_reg <= mi_din[10:0];
+       ecfg_dataout_reg[10:0] <= mi_din[10:0];
 
    assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
    
@@ -347,8 +347,8 @@ module ecfg (/*AUTOARG*/
          `E_REG_SYSCFGCLK:   mi_dout[31:0] <= {24'b0, ecfg_cfgclk_reg[7:0]};
          `E_REG_SYSCOREID:   mi_dout[31:0] <= {{(32-IDW){1'b0}}, ecfg_coreid_reg[IDW-1:0]};
          `E_REG_SYSVERSION:  mi_dout[31:0] <= VERSION;
-         `E_REG_SYSDATAIN:   mi_dout[31:0] <= {20'b0, ecfg_datain_reg[11:0]};
-         `E_REG_SYSDATAOUT:  mi_dout[31:0] <= {20'b0, ecfg_dataout_reg[11:0]};
+         `E_REG_SYSDATAIN:   mi_dout[31:0] <= {21'b0, ecfg_datain_reg[10:0]};
+         `E_REG_SYSDATAOUT:  mi_dout[31:0] <= {21'b0, ecfg_dataout_reg[10:0]};
 	 `E_REG_SYSDEBUG:    mi_dout[31:0] <= ecfg_debug_signals[31:0];
          default:            mi_dout[31:0] <= 32'd0;
        endcase
diff --git a/elink/hdl/elink.v b/elink/hdl/elink.v
index dac967c..d7d2ea3 100644
--- a/elink/hdl/elink.v
+++ b/elink/hdl/elink.v
@@ -656,9 +656,9 @@ module elink(/*AUTOARG*/
    /***********************************************************/
    //TODO: fix decode logic
 
-   assign mi_rd_data[31:0] = (mi_addr[15:14]==2'b00) ? mi_dout_ecfg[31:0]  :
-			     (mi_addr[15:14]==2'b01) ? mi_dout_embox[31:0] :
-			     (mi_addr[15:14]==2'b10) ? mi_dout_rx[31:0]    :
+   assign mi_rd_data[31:0] = (mi_addr[13:12]==2'b00) ? mi_dout_ecfg[31:0]  :
+			     (mi_addr[13:12]==2'b01) ? mi_dout_embox[31:0] :
+			     (mi_addr[13:12]==2'b10) ? mi_dout_rx[31:0]    :
 			      mi_dout_tx[31:0]    ;
    
 endmodule // elink