FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity

Fixing wait circuit in emmu

Browse Source 
- need to consider read/write
- fixing packet parsing, write bit was moved o [0]
This commit is contained in:
Andreas Olofsson 2015-11-13 16:22:23 -05:00
parent a44778b8be
commit 13c523e80c
1 changed files with 20 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
emmu/hdl/emmu.v
View File

@ -20,7 +20,7 @@ module emmu (/*AUTOARG*/
mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out, mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
// Inputs // Inputs
rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr, mi_din, rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr, mi_din,
emesh_access_in, emesh_packet_in, emesh_wait emesh_access_in, emesh_packet_in, emesh_rd_wait, emesh_wr_wait
); );
parameter DW = 32; //data width parameter DW = 32; //data width
parameter AW = 32; //address width parameter AW = 32; //address width
@ -56,7 +56,8 @@ module emmu (/*AUTOARG*/
/*****************************/ /*****************************/
input emesh_access_in; input emesh_access_in;
input [PW-1:0] emesh_packet_in; input [PW-1:0] emesh_packet_in;
input emesh_wait; //BUG?: separate wait fifos? input emesh_rd_wait;
input emesh_wr_wait;
/*****************************/ /*****************************/
/*EMESH OUTPUTS */ /*EMESH OUTPUTS */
@ -76,7 +77,7 @@ module emmu (/*AUTOARG*/
wire [63:0] mi_wr_data; wire [63:0] mi_wr_data;
wire [5:0] mi_wr_vec; wire [5:0] mi_wr_vec;
wire mi_match; wire mi_match;
wire [MW-1:0] emmu_rd_addr; wire [31:0] emmu_rd_addr;
wire write_in; wire write_in;
/*****************************/ /*****************************/
@ -97,8 +98,15 @@ module emmu (/*AUTOARG*/
/*****************************/ /*****************************/
/*MMU READ LOGIC */ /*MMU READ LOGIC */
/*****************************/ /*****************************/
assign write_in = emesh_packet_in[1]; //TODO: packet2emesh p2e (//outputs
assign emmu_rd_addr[MAW-1:0] = emesh_packet_in[39:28]; .write_out (write_in),
.datamode_out (),
.ctrlmode_out (),
.data_out (),
.dstaddr_out (emmu_rd_addr[AW-1:0]),
.srcaddr_out (),
//inputs
.packet_in (emesh_packet_in[PW-1:0]));
memory_dp #(.DW(MW),.AW(MAW)) memory_dp ( memory_dp #(.DW(MW),.AW(MAW)) memory_dp (
// Outputs // Outputs
@ -121,7 +129,7 @@ module emmu (/*AUTOARG*/
//the pushback is needed stall async transmit path //the pushback is needed stall async transmit path
always @ (posedge rd_clk) always @ (posedge rd_clk)
if(~emesh_wait) if(~(emesh_wr_wait & write_in) & ~(emesh_rd_wait & ~write_in))
begin begin
emesh_access_out <= emesh_access_in; emesh_access_out <= emesh_access_in;
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0]; emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];
@ -140,7 +148,7 @@ module emmu (/*AUTOARG*/
endmodule // emmu endmodule // emmu
// Local Variables: // Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../memory/hdl") // verilog-library-directories:("." "../../common/hdl" "../../memory/hdl" "../../emesh/hdl")
// End: // End: