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Adding clockmux2 and clockmux4

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-Cover 99% of all cases clock selectors
This commit is contained in:
aolofsson 2021-07-26 11:44:17 -04:00
parent 10421758bc
commit 15c65d2282
2 changed files with 82 additions and 0 deletions
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36
common/hdl/oh_clockmux2.v Normal file
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//#############################################################################
//# Function: 2:1 Clock Mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockmux2
#(parameter SYN = "TRUE", // synthesizable (or not)
parameter TYPE = "DEFAULT" // implementation type
)
(
input en0, // clkin0 enable (stable high)
input en1, // clkin1 enable (stable high)
input clkin0, // clock input
input clkin1, // clock input
output clkout // clock output
);
generate
if(SYN == "TRUE") begin
assign clkout = en0 & clkin0 |
en1 & clkin1;
end
else begin
oh_clockmux2 #(.TYPE(TYPE))
oh_clockmux2(// Outputs
.clkout (clkout),
// Inputs
.en0 (en0),
.en1 (en1),
.clkin0 (clkin0),
.clkin1 (clkin1));
end
endgenerate
endmodule

46
common/hdl/oh_clockmux4.v Normal file
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//#############################################################################
//# Function: 4:1 Clock Mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockmux4
#(parameter SYN = "TRUE", // synthesizable (or not)
parameter TYPE = "DEFAULT" // implementation type
)
(
input en0, // clkin0 enable (stable high)
input en1, // clkin1 enable (stable high)
input en2, // clkin1 enable (stable high)
input en3, // clkin1 enable (stable high)
input clkin0, // clock input
input clkin1, // clock input
input clkin2, // clock input
input clkin3, // clock input
output clkout // clock output
);
generate
if(SYN == "TRUE") begin
assign clkout = en0 & clkin0 |
en1 & clkin1 |
en2 & clkin2 |
en3 & clkin3;
end
else begin
oh_clockmux4 #(.TYPE(TYPE))
oh_clockmux4(// Outputs
.clkout (clkout),
// Inputs
.en0 (en0),
.en1 (en1),
.en2 (en2),
.en3 (en3),
.clkin0 (clkin0),
.clkin1 (clkin1),
.clkin2 (clkin2),
.clkin3 (clkin3));
end
endgenerate
endmodule