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Make tech_cfg an inout so it can expose tieoffs

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This commit is contained in:
Noah Moroze 2021-10-07 18:31:34 +00:00
parent eeb0b784c4
commit 172c1f8732
2 changed files with 5 additions and 5 deletions
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8
padring/hdl/oh_padring.v
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@ -49,7 +49,7 @@ module oh_padring
input [NO_GPIO*8-1:0] no_cfg, // config
input [NO_GPIO-1:0] no_ie, // input enable
input [NO_GPIO-1:0] no_oen, // output enable (bar)
input [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
inout [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
//SOUTH
inout [SO_DOMAINS-1:0] so_vddio,
inout [SO_DOMAINS-1:0] so_vssio,
@ -59,7 +59,7 @@ module oh_padring
input [SO_GPIO*8-1:0] so_cfg, // config
input [SO_GPIO-1:0] so_ie, // input enable
input [SO_GPIO-1:0] so_oen, // output enable (bar)
input [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
inout [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
//EAST
inout [EA_DOMAINS-1:0] ea_vddio,
inout [EA_DOMAINS-1:0] ea_vssio,
@ -69,7 +69,7 @@ module oh_padring
input [EA_GPIO*8-1:0] ea_cfg, // config
input [EA_GPIO-1:0] ea_ie, // input enable
input [EA_GPIO-1:0] ea_oen, // output enable (bar)
input [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
inout [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
//WEST
inout [WE_DOMAINS-1:0] we_vddio,
inout [WE_DOMAINS-1:0] we_vssio,
@ -79,7 +79,7 @@ module oh_padring
input [WE_GPIO*8-1:0] we_cfg, // config
input [WE_GPIO-1:0] we_ie, // input enable
input [WE_GPIO-1:0] we_oen, // output enable (bar)
input [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
inout [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
);

2
padring/hdl/oh_pads_domain.v
View File

@ -35,7 +35,7 @@ module oh_pads_domain
input [NGPIO-1:0] oen, // output enable (bar)
input [NGPIO-1:0] ie, // input enable
input [NGPIO*8-1:0] cfg, // io config
input [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
inout [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
);
generate