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Solved read response bug. MATMUL WORKS!!!!
- Turns out I was debugging ghosts for ~1 day today. Everything was working in simulation but nothing works in the FPGA. Since I was only changing small logic stuff, I didn't bother checking the warning messages in Viviado. Turns out for some reason it was throwing away some logic and disconnecting all the important rr signals - This is where I was making changes, but I still can't figure out what exactly was happening...doesn't make sense. Either there is a bug in icarus or in vivado, this shouldn't happen!
This commit is contained in:
Andreas Olofsson
parent
08f5d28ed4
commit
1890657d6d
@ -155,15 +155,22 @@ module emaxi(/*autoarg*/
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reg txrr_access;
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reg [31:0] txrr_data;
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reg [31:0] txrr_srcaddr;
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reg [1:0] txrr_datamode;
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reg [3:0] txrr_ctrlmode;
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reg [31:0] txrr_dstaddr;
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reg [63:0] m_axi_rdata_fifo;
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reg txrr_access_fifo;
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//wires
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wire aw_go;
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wire w_go;
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wire readinfo_wren;
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wire readinfo_full;
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wire [47:0] readinfo_out;
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wire [47:0] readinfo_in;
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wire [40:0] readinfo_out;
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wire [40:0] readinfo_in;
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wire awvalid_in;
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wire [1:0] rxwr_datamode;
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@ -176,6 +183,16 @@ module emaxi(/*autoarg*/
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wire [AW-1:0] rxrd_dstaddr;
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wire [AW-1:0] rxrd_srcaddr;
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wire [1:0] txrr_datamode_fifo;
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wire [3:0] txrr_ctrlmode_fifo;
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wire [31:0] txrr_dstaddr_fifo;
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wire [2:0] txrr_alignaddr_fifo;
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wire [103:0] packet_out;
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wire fifo_prog_full;
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wire fifo_full;
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wire fifo_rd_en;
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wire fifo_wr_en;
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//#########################################################################
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//EMESH 2 PACKET CONVERSION
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//#########################################################################
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@ -388,6 +405,7 @@ module emaxi(/*autoarg*/
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end
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end // else: !if(~m_axi_aresetn)
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//#########################################################################
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//Read request channel
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//#########################################################################
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@ -395,14 +413,11 @@ module emaxi(/*autoarg*/
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//2. use src address to match with writes coming back
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//3. Assumes in order returns
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assign readinfo_in[47:0] =
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{
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7'b0,
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rxrd_srcaddr[31:0],//40:9
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rxrd_dstaddr[2:0], //8:6
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rxrd_ctrlmode[3:0],//5:2
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rxrd_datamode[1:0] //1:0
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};
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assign readinfo_in[40:0] = {rxrd_srcaddr[31:0],//40:9
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rxrd_dstaddr[2:0], //8:6
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rxrd_ctrlmode[3:0],//5:2
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rxrd_datamode[1:0] //1:0
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};
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//Rest synchronization (for safety, assume incoming reset is async)
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@ -412,60 +427,28 @@ module emaxi(/*autoarg*/
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.din (m_axi_aresetn)
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);
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//Synchronous FIFO for read transactions
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//Synchronous FIFO for read transactions
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//TODO: We don't have a way of testing this, since we don't have a model that will accept enough
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//transactions (need an actual axi implementation that doesn't stall on every read)
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//SOLUTION: Put in the bullet proof async fifo and hope...
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wire [PW-1:0] packet_out;
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wire fifo_prog_full;
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wire fifo_full;
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defparam fifo.DW = 104;
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defparam fifo.DEPTH = 32;
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defparam fifo.WAIT = 0;
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fifo_async fifo (.full (fifo_full),
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.prog_full (fifo_prog_full),
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.dout (packet_out[PW-1:0]),
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.empty (),
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.valid (),
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// Inputs
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.rst (~sync_nreset),
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.wr_clk (m_axi_aclk),
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.rd_clk (m_axi_aclk),
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.wr_en (fifo_wr_en),
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.din ({56'b0,readinfo_in[47:0]}),
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.rd_en (fifo_rd_en)
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);
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assign readinfo_out[47:0] = packet_out[47:0];
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/*
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fifo_sync
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#(
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// parameters
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.AW (5),
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.DW (48))
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fifo_readinfo_i
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(
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// outputs
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.rd_data (readinfo_out[47:0]),
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.rd_empty (),
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.wr_full (readinfo_full),
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// inputs
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.clk (m_axi_aclk),
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.reset (~sync_nreset),
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.wr_data (readinfo_in[47:0]),
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.wr_en (m_axi_arvalid & m_axi_arready),
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.rd_en (m_axi_rready & m_axi_rvalid)
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);
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*/
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fifo_async #(.DW(104), .DEPTH(32))
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fifo_async (.full (fifo_full),
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.prog_full (fifo_prog_full),
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.dout (packet_out[103:0]),
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.empty (),
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.valid (),
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// Inputs
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.rst (~sync_nreset),
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.wr_clk (m_axi_aclk),
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.rd_clk (m_axi_aclk),
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.wr_en (fifo_wr_en),
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.din ({63'b0,readinfo_in[40:0]}),
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.rd_en (fifo_rd_en)
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);
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assign txrr_datamode_fifo[1:0] = packet_out[1:0];
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assign txrr_ctrlmode_fifo[3:0] = packet_out[5:2];
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assign txrr_alignaddr_fifo[2:0] = packet_out[8:6];
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assign txrr_dstaddr_fifo[31:0] = packet_out[40:9];
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//###################################################################
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//Read address channel
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//###################################################################
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@ -474,91 +457,73 @@ module emaxi(/*autoarg*/
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assign m_axi_arsize[2:0] = {1'b0, rxrd_datamode[1:0]};
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assign m_axi_arlen[7:0] = 8'd0;
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assign m_axi_arvalid = rxrd_access & ~fifo_prog_full; //BUG& ~txrr_wait & ~fifo_prog_full; //remove
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assign rxrd_wait = ~m_axi_arready | fifo_prog_full;//BUG| txrr_wait
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assign fifo_wr_en = m_axi_arvalid & m_axi_arready ;
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assign fifo_rd_en = m_axi_rready & m_axi_rvalid;//BUG & ~txrr_wait
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assign rxrd_wait = ~m_axi_arready | fifo_prog_full;//BUG| txrr_wait
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assign fifo_rd_en = m_axi_rvalid & m_axi_rready;//BUG & ~txrr_wait
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//#################################################################
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//Read response channel
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//#################################################################
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assign m_axi_rready = ~txrr_wait; //BUG!: 1'b1
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wire [1:0] txrr_datamode_fifo;
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wire [3:0] txrr_ctrlmode_fifo;
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wire [31:0] txrr_dstaddr_fifo;
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wire [2:0] txrr_srcaddr_fifo;
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reg [1:0] txrr_datamode;
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reg [3:0] txrr_ctrlmode;
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reg [31:0] txrr_dstaddr;
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assign txrr_datamode_fifo[1:0] = readinfo_out[1:0];
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assign txrr_ctrlmode_fifo[3:0] = readinfo_out[5:2];
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assign txrr_srcaddr_fifo[2:0] = readinfo_out[8:6];
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assign txrr_dstaddr_fifo[31:0] = readinfo_out[40:9];
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//Pipeline axi transaction to account for FIFO read latency
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reg [63:0] m_axi_rdata_fifo;
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reg txrr_access_fifo;
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always @( posedge m_axi_aclk)
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always @ (posedge m_axi_aclk)
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if(!m_axi_aresetn)
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begin
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txrr_access_fifo <= 1'b0;
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txrr_access_fifo <= 1'b0;
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txrr_access <= 1'b0;
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end
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else
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begin
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txrr_access_fifo <= fifo_rd_en;
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m_axi_rdata_fifo[63:0] <= m_axi_rdata[63:0];
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txrr_access_fifo <= fifo_rd_en;
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txrr_access <= txrr_access_fifo;
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end
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//Alignment Mux (one cycle)
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always @ (posedge m_axi_aclk )
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if(!m_axi_aresetn)
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begin
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txrr_access <= 1'b0;
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end
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else
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begin
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txrr_access <= txrr_access_fifo;
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txrr_datamode[1:0] <= txrr_datamode_fifo[1:0];
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txrr_ctrlmode[3:0] <= txrr_ctrlmode_fifo[3:0];
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txrr_dstaddr[31:0] <= txrr_dstaddr_fifo[31:0];
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//all data needs to be right aligned
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//(this is due to the Epiphany right aligning all words)
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case(txrr_datamode_fifo[1:0])//datamode
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2'd0: // byte read
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case(txrr_srcaddr_fifo[2:0])
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3'd0: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]};
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3'd1: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[15:8]};
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3'd2: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[23:16]};
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3'd3: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[31:24]};
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3'd4: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[39:32]};
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3'd5: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[47:40]};
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3'd6: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[55:48]};
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3'd7: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[63:56]};
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default: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]};
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endcase
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2'd1: // 16b hword
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case(txrr_srcaddr_fifo[2:1])
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2'd0: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]};
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2'd1: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[31:16]};
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2'd2: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[47:32]};
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2'd3: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[63:48]};
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default: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]};
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endcase
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2'd2: // 32b word
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if(txrr_srcaddr_fifo[2])
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txrr_data[31:0] <= m_axi_rdata_fifo[63:32];
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else
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txrr_data[31:0] <= m_axi_rdata_fifo[31:0];
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// 64b word already defined by defaults above
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2'd3:
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begin // 64b dword
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txrr_data[31:0] <= m_axi_rdata_fifo[31:0];
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txrr_srcaddr[31:0] <= m_axi_rdata_fifo[63:32];
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end
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endcase
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end // else: !if( ~m_axi_aresetn )
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always @ (posedge m_axi_aclk)
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begin
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m_axi_rdata_fifo[63:0] <= m_axi_rdata[63:0];
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txrr_datamode[1:0] <= txrr_datamode_fifo[1:0];
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txrr_ctrlmode[3:0] <= txrr_ctrlmode_fifo[3:0];
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txrr_dstaddr[31:0] <= txrr_dstaddr_fifo[31:0];
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//all data needs to be right aligned
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//(this is due to the Epiphany right aligning all words)
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case(txrr_datamode_fifo[1:0])//datamode
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2'd0: // byte read
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case(txrr_alignaddr_fifo[2:0])
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3'd0: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]};
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3'd1: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[15:8]};
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3'd2: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[23:16]};
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3'd3: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[31:24]};
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3'd4: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[39:32]};
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3'd5: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[47:40]};
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3'd6: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[55:48]};
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3'd7: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[63:56]};
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default: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]};
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endcase
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2'd1: // 16b hword
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case(txrr_alignaddr_fifo[2:1])
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2'd0: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]};
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2'd1: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[31:16]};
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2'd2: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[47:32]};
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2'd3: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[63:48]};
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default: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]};
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endcase
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2'd2: // 32b word
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begin
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if(txrr_alignaddr_fifo[2])
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txrr_data[31:0] <= m_axi_rdata_fifo[63:32];
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else
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txrr_data[31:0] <= m_axi_rdata_fifo[31:0];
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end
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// 64b word already defined by defaults above
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2'd3:
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begin // 64b dword
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txrr_data[31:0] <= m_axi_rdata_fifo[31:0];
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txrr_srcaddr[31:0] <= m_axi_rdata_fifo[63:32];
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end
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endcase
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end // always @ (posedge m_axi_aclk1 )
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endmodule // emaxi
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// Local Variables:
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