From 1890657d6d4ee6e085b5c7065e62f29b13db3bb6 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Wed, 25 Nov 2015 23:50:29 -0500 Subject: [PATCH] Solved read response bug. MATMUL WORKS!!!! - Turns out I was debugging ghosts for ~1 day today. Everything was working in simulation but nothing works in the FPGA. Since I was only changing small logic stuff, I didn't bother checking the warning messages in Viviado. Turns out for some reason it was throwing away some logic and disconnecting all the important rr signals - This is where I was making changes, but I still can't figure out what exactly was happening...doesn't make sense. Either there is a bug in icarus or in vivado, this shouldn't happen! --- elink/hdl/emaxi.v | 229 ++++++++++++++++++++-------------------------- 1 file changed, 97 insertions(+), 132 deletions(-) diff --git a/elink/hdl/emaxi.v b/elink/hdl/emaxi.v index 007555a..a12b269 100644 --- a/elink/hdl/emaxi.v +++ b/elink/hdl/emaxi.v @@ -155,15 +155,22 @@ module emaxi(/*autoarg*/ reg txrr_access; reg [31:0] txrr_data; reg [31:0] txrr_srcaddr; + reg [1:0] txrr_datamode; + reg [3:0] txrr_ctrlmode; + reg [31:0] txrr_dstaddr; + reg [63:0] m_axi_rdata_fifo; + reg txrr_access_fifo; + + + //wires wire aw_go; wire w_go; wire readinfo_wren; wire readinfo_full; - wire [47:0] readinfo_out; - wire [47:0] readinfo_in; - + wire [40:0] readinfo_out; + wire [40:0] readinfo_in; wire awvalid_in; wire [1:0] rxwr_datamode; @@ -176,6 +183,16 @@ module emaxi(/*autoarg*/ wire [AW-1:0] rxrd_dstaddr; wire [AW-1:0] rxrd_srcaddr; + wire [1:0] txrr_datamode_fifo; + wire [3:0] txrr_ctrlmode_fifo; + wire [31:0] txrr_dstaddr_fifo; + wire [2:0] txrr_alignaddr_fifo; + wire [103:0] packet_out; + wire fifo_prog_full; + wire fifo_full; + wire fifo_rd_en; + wire fifo_wr_en; + //######################################################################### //EMESH 2 PACKET CONVERSION //######################################################################### @@ -388,6 +405,7 @@ module emaxi(/*autoarg*/ end end // else: !if(~m_axi_aresetn) + //######################################################################### //Read request channel //######################################################################### @@ -395,14 +413,11 @@ module emaxi(/*autoarg*/ //2. use src address to match with writes coming back //3. Assumes in order returns - assign readinfo_in[47:0] = - { - 7'b0, - rxrd_srcaddr[31:0],//40:9 - rxrd_dstaddr[2:0], //8:6 - rxrd_ctrlmode[3:0],//5:2 - rxrd_datamode[1:0] //1:0 - }; + assign readinfo_in[40:0] = {rxrd_srcaddr[31:0],//40:9 + rxrd_dstaddr[2:0], //8:6 + rxrd_ctrlmode[3:0],//5:2 + rxrd_datamode[1:0] //1:0 + }; //Rest synchronization (for safety, assume incoming reset is async) @@ -412,60 +427,28 @@ module emaxi(/*autoarg*/ .din (m_axi_aresetn) ); - //Synchronous FIFO for read transactions + //Synchronous FIFO for read transactions - //TODO: We don't have a way of testing this, since we don't have a model that will accept enough - //transactions (need an actual axi implementation that doesn't stall on every read) - //SOLUTION: Put in the bullet proof async fifo and hope... - - - wire [PW-1:0] packet_out; - wire fifo_prog_full; - wire fifo_full; - defparam fifo.DW = 104; - defparam fifo.DEPTH = 32; - defparam fifo.WAIT = 0; - - fifo_async fifo (.full (fifo_full), - .prog_full (fifo_prog_full), - .dout (packet_out[PW-1:0]), - .empty (), - .valid (), - // Inputs - .rst (~sync_nreset), - .wr_clk (m_axi_aclk), - .rd_clk (m_axi_aclk), - .wr_en (fifo_wr_en), - .din ({56'b0,readinfo_in[47:0]}), - .rd_en (fifo_rd_en) - ); - - assign readinfo_out[47:0] = packet_out[47:0]; - -/* - - fifo_sync - #( - // parameters - .AW (5), - .DW (48)) - fifo_readinfo_i - ( - // outputs - .rd_data (readinfo_out[47:0]), - .rd_empty (), - .wr_full (readinfo_full), - // inputs - .clk (m_axi_aclk), - .reset (~sync_nreset), - .wr_data (readinfo_in[47:0]), - .wr_en (m_axi_arvalid & m_axi_arready), - .rd_en (m_axi_rready & m_axi_rvalid) - ); -*/ - - + fifo_async #(.DW(104), .DEPTH(32)) + fifo_async (.full (fifo_full), + .prog_full (fifo_prog_full), + .dout (packet_out[103:0]), + .empty (), + .valid (), + // Inputs + .rst (~sync_nreset), + .wr_clk (m_axi_aclk), + .rd_clk (m_axi_aclk), + .wr_en (fifo_wr_en), + .din ({63'b0,readinfo_in[40:0]}), + .rd_en (fifo_rd_en) + ); + assign txrr_datamode_fifo[1:0] = packet_out[1:0]; + assign txrr_ctrlmode_fifo[3:0] = packet_out[5:2]; + assign txrr_alignaddr_fifo[2:0] = packet_out[8:6]; + assign txrr_dstaddr_fifo[31:0] = packet_out[40:9]; + //################################################################### //Read address channel //################################################################### @@ -474,91 +457,73 @@ module emaxi(/*autoarg*/ assign m_axi_arsize[2:0] = {1'b0, rxrd_datamode[1:0]}; assign m_axi_arlen[7:0] = 8'd0; assign m_axi_arvalid = rxrd_access & ~fifo_prog_full; //BUG& ~txrr_wait & ~fifo_prog_full; //remove - assign rxrd_wait = ~m_axi_arready | fifo_prog_full;//BUG| txrr_wait assign fifo_wr_en = m_axi_arvalid & m_axi_arready ; - assign fifo_rd_en = m_axi_rready & m_axi_rvalid;//BUG & ~txrr_wait + assign rxrd_wait = ~m_axi_arready | fifo_prog_full;//BUG| txrr_wait + assign fifo_rd_en = m_axi_rvalid & m_axi_rready;//BUG & ~txrr_wait //################################################################# //Read response channel //################################################################# assign m_axi_rready = ~txrr_wait; //BUG!: 1'b1 - wire [1:0] txrr_datamode_fifo; - wire [3:0] txrr_ctrlmode_fifo; - wire [31:0] txrr_dstaddr_fifo; - wire [2:0] txrr_srcaddr_fifo; - reg [1:0] txrr_datamode; - reg [3:0] txrr_ctrlmode; - reg [31:0] txrr_dstaddr; - - assign txrr_datamode_fifo[1:0] = readinfo_out[1:0]; - assign txrr_ctrlmode_fifo[3:0] = readinfo_out[5:2]; - assign txrr_srcaddr_fifo[2:0] = readinfo_out[8:6]; - assign txrr_dstaddr_fifo[31:0] = readinfo_out[40:9]; - //Pipeline axi transaction to account for FIFO read latency - reg [63:0] m_axi_rdata_fifo; - reg txrr_access_fifo; - always @( posedge m_axi_aclk) + always @ (posedge m_axi_aclk) if(!m_axi_aresetn) begin - txrr_access_fifo <= 1'b0; + txrr_access_fifo <= 1'b0; + txrr_access <= 1'b0; end else begin - txrr_access_fifo <= fifo_rd_en; - m_axi_rdata_fifo[63:0] <= m_axi_rdata[63:0]; + txrr_access_fifo <= fifo_rd_en; + txrr_access <= txrr_access_fifo; end //Alignment Mux (one cycle) - always @ (posedge m_axi_aclk ) - if(!m_axi_aresetn) - begin - txrr_access <= 1'b0; - end - else - begin - txrr_access <= txrr_access_fifo; - txrr_datamode[1:0] <= txrr_datamode_fifo[1:0]; - txrr_ctrlmode[3:0] <= txrr_ctrlmode_fifo[3:0]; - txrr_dstaddr[31:0] <= txrr_dstaddr_fifo[31:0]; - //all data needs to be right aligned - //(this is due to the Epiphany right aligning all words) - case(txrr_datamode_fifo[1:0])//datamode - 2'd0: // byte read - case(txrr_srcaddr_fifo[2:0]) - 3'd0: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]}; - 3'd1: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[15:8]}; - 3'd2: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[23:16]}; - 3'd3: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[31:24]}; - 3'd4: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[39:32]}; - 3'd5: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[47:40]}; - 3'd6: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[55:48]}; - 3'd7: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[63:56]}; - default: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]}; - endcase - 2'd1: // 16b hword - case(txrr_srcaddr_fifo[2:1]) - 2'd0: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]}; - 2'd1: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[31:16]}; - 2'd2: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[47:32]}; - 2'd3: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[63:48]}; - default: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]}; - endcase - 2'd2: // 32b word - if(txrr_srcaddr_fifo[2]) - txrr_data[31:0] <= m_axi_rdata_fifo[63:32]; - else - txrr_data[31:0] <= m_axi_rdata_fifo[31:0]; - // 64b word already defined by defaults above - 2'd3: - begin // 64b dword - txrr_data[31:0] <= m_axi_rdata_fifo[31:0]; - txrr_srcaddr[31:0] <= m_axi_rdata_fifo[63:32]; - end - endcase - end // else: !if( ~m_axi_aresetn ) - + always @ (posedge m_axi_aclk) + begin + m_axi_rdata_fifo[63:0] <= m_axi_rdata[63:0]; + txrr_datamode[1:0] <= txrr_datamode_fifo[1:0]; + txrr_ctrlmode[3:0] <= txrr_ctrlmode_fifo[3:0]; + txrr_dstaddr[31:0] <= txrr_dstaddr_fifo[31:0]; + //all data needs to be right aligned + //(this is due to the Epiphany right aligning all words) + case(txrr_datamode_fifo[1:0])//datamode + 2'd0: // byte read + case(txrr_alignaddr_fifo[2:0]) + 3'd0: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]}; + 3'd1: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[15:8]}; + 3'd2: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[23:16]}; + 3'd3: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[31:24]}; + 3'd4: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[39:32]}; + 3'd5: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[47:40]}; + 3'd6: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[55:48]}; + 3'd7: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[63:56]}; + default: txrr_data[31:0] <= {24'b0,m_axi_rdata_fifo[7:0]}; + endcase + 2'd1: // 16b hword + case(txrr_alignaddr_fifo[2:1]) + 2'd0: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]}; + 2'd1: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[31:16]}; + 2'd2: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[47:32]}; + 2'd3: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[63:48]}; + default: txrr_data[31:0] <= {16'b0,m_axi_rdata_fifo[15:0]}; + endcase + 2'd2: // 32b word + begin + if(txrr_alignaddr_fifo[2]) + txrr_data[31:0] <= m_axi_rdata_fifo[63:32]; + else + txrr_data[31:0] <= m_axi_rdata_fifo[31:0]; + end + // 64b word already defined by defaults above + 2'd3: + begin // 64b dword + txrr_data[31:0] <= m_axi_rdata_fifo[31:0]; + txrr_srcaddr[31:0] <= m_axi_rdata_fifo[63:32]; + end + endcase + end // always @ (posedge m_axi_aclk1 ) endmodule // emaxi // Local Variables: