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Adding documentation to elink top level module
This commit is contained in:
Andreas Olofsson
parent
4c06e4be61
commit
18b2c489b0
129
elink/hdl/ecfg.v
129
elink/hdl/ecfg.v
@ -1,133 +1,8 @@
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/*
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########################################################################
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EPIPHANY CONFIGURATION REGISTER (32bit access)
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ELINK CONFIGURATION REGISTER FILE
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########################################################################
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-------------------------------------------------------------
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ESYSRESET ***Elink reset***
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[0] 0 - elink active
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1 - elink in reset
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-------------------------------------------------------------
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ESYSTX ***Elink transmitter configuration***
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[0] 0 - link TX disable
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1 - link TX enable
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[1] 0 - normal pass through transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio drive mode
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10 - reserved
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11 - reserved
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[7:4] Transmit control mode for eMesh
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[8] AXI slave read timeout enable
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-------------------------------------------------------------
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ESYSRX ***Elink receiver configuration***
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[0] 0 - link RX disable
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1 - link RX enable
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[1] 0 - normal transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio sample mode (drive rd wait pins from registers)
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10 - reserved
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11 - reserved
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-------------------------------------------------------------
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ESYSCLK ***Epiphany clock frequency setting***
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[0] Enable CCLK
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[1] Enable TX_LCLK
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[2] CCLK PLL bypass mode (cclk is set to clkin)
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[3] LCLK PLL bypass mode (lclk is set to clkin)
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[7:4] CCLK PLL Divider (1<<reg)
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0000 - CLKIN/1
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0001 - CLKIN/2
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0010 - CLKIN/4
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0011 - CLKIN/8
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0100 - CLKIN/16
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0101 - CLKIN/32
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0110 - CLKIN/64
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0111 - CLKIN/128
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1xxx - RESERVED
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[11:8] Elink PLL Divider (1<<reg)
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0000 - CLKIN/1
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0001 - CLKIN/2
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0010 - CLKIN/4
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0011 - CLKIN/8
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0100 - CLKIN/16
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0101 - CLKIN/32
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0110 - CLKIN/64
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0111 - CLKIN/128
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1xxx - RESERVED
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[15:12] PLL Frequency
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0000 -
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0001 -
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0010 -
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0011 -
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0100 -
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0101 -
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0110 -
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0111 -
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1000 -
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1001 -
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1010 -
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1011 -
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1100 -
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1101 -
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1110 -
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1111 -
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-------------------------------------------------------------
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ESYSCOREID ***CORE ID***
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[5:0] Column ID-->default at powerup/reset
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[11:6] Row ID
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-------------------------------------------------------------
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ESYSLATFORM ***Platform ID (read only)***
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[7:0] Platform model number
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-------------------------------------------------------------
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ESYSDATAIN ***Data on elink input pins
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[7:0] rx_data[7:0]
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[8] tx_frame
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[9] tx_wait_rd
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[10] tx_wait_wr
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-------------------------------------------------------------
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ESYSDATAOUT ***Data on eLink output pins
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[7:0] tx_data[7:0]
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[8] tx_frame
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[9] rx_wait_rd
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[10] rx_wait_wr
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-------------------------------------------------------------
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ESYSDEBUG ***Various debug signals from elink
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[31] embox_not_empty
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//RX signals
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[30] emesh_rx_rd_wait
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[29] emesh_rx_wr_wait
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[28] esaxi_emrr_rd_en
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[27] emrr_full
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[26] emrr_progfull
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[25] emrr_wr_en
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[24] emaxi_emrq_rd_en
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[23] emrq_progfull
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[22] emrq_wr_en
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[21] emaxi_emwr_rd_en
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[20] emwr_progfull
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[19] emwr_wr_en (rx)
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//TX signals
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[18] e_tx_rd_wait
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[17] e_tx_wr_wait
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[16] emrr_rd_en
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[15] emaxi_emrr_prog_full
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[14] emaxi_emrr_wr_en
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[13] emrq_rd_en
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[12 esaxi_emrq_prog_full
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[11] esaxi_emrq_wr_en
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[10] emwr_rd_en
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[9] esaxi_emwr_prog_full
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[8] esaxi_emwr_wr_en
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##########Sticky signals below#############
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[7] reserved
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[6] emrr_full (rx)
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[5] emrq_full (rx)
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[4] emwr_full (rx)
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[3] emaxi_emrr_full (tx)
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[2] esaxi_emrq_full (tx)
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[1] esaxi_emwr_full (tx)
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[0] embox_full (mailbox)
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########################################################################
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*/
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module ecfg (/*AUTOARG*/
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@ -1,3 +1,226 @@
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/*
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########################################################################
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DESCRIPTION
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########################################################################
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The "eLink" is a low latency chip to chip interface used by for communication
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between Epiphany chips and FPGAs. The interface "should" achieve a peak
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throughput of 8 Gbit/s in FPGAs with 24 available LVDS signal pairs.
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SIGNAL | DESCRIPTION
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---------------|--------------
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TXO_FRAME | Packet framing signal. Rising edge signals new packet.
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TXO_LCLK | A clock aligned in the center of the data eye
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TXO_DATA[7:0] | Dual data rate (DDR) that transmits packet
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TXI_RD_WAIT | Push back signal for read transactions
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TXI_WR_WAIT | Push back signal for write transactions
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A symmetrical set of signals exit on the receiver side.
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The elink has a 64 bit data AXI master and 32-bit data AXI slave interface
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for connecting to a standard AXI network.
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PACKET SUBFIELD | DESCRIPTION
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----------------|----------------
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access | Indicates a valid packet
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write | A write transaction. Access & ~write indicates a read.
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datamode[1:0] | Datasize (00=8b,01=16b,10=32b,11=64b)
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ctrlmode[3:0] | Various packet modes for the Epiphany chip
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dstraddr[31:0] | Address for write, read-request, or read-respones transaction
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data[31:0] | Data for write transation, return data for read response
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srcaddr[31:0] | Return address for read-request, upper data for 64 bit write
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More gory details:
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The elink was born out of a need to connect multiple Epiphany chips together
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and uses the eMesh 104 bit atomic packet structure for communication.
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The eMesh atomic patcket consists of the following sub fields.
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The number of bytes to be received is determined by the data of the first
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“valid” byte (byte0) and the level of the FRAME signal. The data captured
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on the rising edge of the LCLK is considered to be byte0 if the FRAME control
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captured at the same cycle (rising edge) is high but was low at the rising
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edge of the previous LCLK cycle. The cycle after the last byte of the
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transaction (byte8 or byte12) will determine if the receiver should go into
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data streaming mode based on the level of the FRAME control signal. If the
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FRAME signal is low, the transaction is complete. If the FRAME control
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signal stays high, the eLink goes into “streaming mode”, meaning that the
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last byte of the previous transaction (byte8 or byte12) will be followed
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by byte5 of the new transaction.
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The WAIT_RD and WAIT_WR signals are used to stall transmission when a receiver
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is unable to accept more transactions. The receiver will raise its WAIT output
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signal on the second rising edge of LCLK input following the capturing rising
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edge of the last transaction byte (byte8 or byte12) but will be ready to
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accept one more full transaction (byte0 through byte8/byte12). The WAIT
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signal seen by the transmitter is assumed to be of the “unspecified” phase
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delay (while still of the LCLK clock period) and therefore has to be sampled
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with the two-cycle synchronizer. Once synchronized to the transmitter's LCLK
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clock domain, the WAIT control signals will prevent new transaction from
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being transmitted. If the transaction is in the middle of the transmission
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when the synchronized WAIT control goes high, the transmission process is to
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be completed without interruption. The txo_* interface driven out from the
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E16G301 uses a divided version of the core cock frequency (RXI_WE_CCLK_{P,N}).
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The transmit clock is automatically aligned in the middle of the data eye
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by the eLink on chip transmit logic. The receiver logic assumes the clock is
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aligned at the center of the receiver data eye. The “wait” signals are used
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to indicate to the transmit logic that no more transactions can be received
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because the receiver buffer full.
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########################################################################
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ELINK MEMORY MAP
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########################################################################
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The elink has an parameter called 'ELINKID' that can be configured by
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the module instantiating the elink.
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REGISTER | ADDRESS | NOTES
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------------| -------------|------
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ESYSRESET | 0xF0000 | Soft reset
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ESYSTX | 0xF0004 | Elink tranmit config
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ESYSRX | 0xF0008 | Elink receiver config
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ESYSCLK | 0xF000C | Clock config
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ESYSCOREID | 0xF0010 | ID to drive to Epiphany chip
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ESYSVERSION | 0xF0014 | Platform version
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ESYSDATAIN | 0xF0018 | Direct data from elink receiver
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ESYSDATAOUT | 0xF001C | Direct data for elink transmitter
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ESYSDEBUG | 0xF0020 | Various debug signals
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---------------------------------------------------------------------------
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EMBOXLO | 0xC0004 | Lower 32 bits of 64 bit wide mail box fifo
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EMBOXHI | 0xC0008 | Upper 32 bits of 64 bit wide mail box fifo
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---------------------------------------------------------------------------
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ESYSMMURX | 0xE0000 | Start of receiver MMU lookup table
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ESYSMMUTX | 0xD0000 | Start of transmit MMU lookup table (tbd)
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########################################################################
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ELINK CONFIGURATION REGISTER (32bit access)
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########################################################################
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-------------------------------------------------------------
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ESYSRESET ***Elink reset***
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[0] 0 - elink active
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1 - elink in reset
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-------------------------------------------------------------
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ESYSTX ***Elink transmitter configuration***
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[0] 0 - link TX disable
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1 - link TX enable
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[1] 0 - normal pass through transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio drive mode
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10 - reserved
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11 - reserved
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[7:4] Transmit control mode for eMesh
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[8] AXI slave read timeout enable
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-------------------------------------------------------------
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ESYSRX ***Elink receiver configuration***
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[0] 0 - link RX disable
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1 - link RX enable
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[1] 0 - normal transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio sample mode (drive rd wait pins from registers)
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10 - reserved
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11 - reserved
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-------------------------------------------------------------
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ESYSCLK ***Epiphany clock frequency setting***
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[0] Enable CCLK
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[1] Enable TX_LCLK
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[2] CCLK PLL bypass mode (cclk is set to clkin)
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[3] LCLK PLL bypass mode (lclk is set to clkin)
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[7:4] CCLK PLL Divider (1<<reg)
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0000 - CLKIN/1
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0001 - CLKIN/2
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0010 - CLKIN/4
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0011 - CLKIN/8
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0100 - CLKIN/16
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0101 - CLKIN/32
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0110 - CLKIN/64
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0111 - CLKIN/128
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1xxx - RESERVED
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[11:8] Elink PLL Divider (1<<reg)
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0000 - CLKIN/1
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0001 - CLKIN/2
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0010 - CLKIN/4
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0011 - CLKIN/8
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0100 - CLKIN/16
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0101 - CLKIN/32
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0110 - CLKIN/64
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0111 - CLKIN/128
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1xxx - RESERVED
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[15:12] PLL Frequency
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0000 -
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0001 -
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0010 -
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0011 -
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0100 -
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0101 -
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0110 -
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0111 -
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1000 -
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1001 -
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1010 -
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1011 -
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1100 -
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1101 -
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1110 -
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1111 -
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-------------------------------------------------------------
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ESYSCOREID ***CORE ID***
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[5:0] Column ID-->default at powerup/reset
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[11:6] Row ID
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-------------------------------------------------------------
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ESYSLATFORM ***Platform ID (read only)***
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[7:0] Platform model number
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-------------------------------------------------------------
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ESYSDATAIN ***Data on elink input pins
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[7:0] rx_data[7:0]
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[8] tx_frame
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[9] tx_wait_rd
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[10] tx_wait_wr
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-------------------------------------------------------------
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ESYSDATAOUT ***Data on eLink output pins
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[7:0] tx_data[7:0]
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[8] tx_frame
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[9] rx_wait_rd
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[10] rx_wait_wr
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-------------------------------------------------------------
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ESYSDEBUG ***Various debug signals from elink
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[31] embox_not_empty
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//RX signals
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[30] emesh_rx_rd_wait
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[29] emesh_rx_wr_wait
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[28] esaxi_emrr_rd_en
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[27] emrr_full
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[26] emrr_progfull
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[25] emrr_wr_en
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[24] emaxi_emrq_rd_en
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[23] emrq_progfull
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[22] emrq_wr_en
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[21] emaxi_emwr_rd_en
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[20] emwr_progfull
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[19] emwr_wr_en (rx)
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//TX signals
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[18] e_tx_rd_wait
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[17] e_tx_wr_wait
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[16] emrr_rd_en
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[15] emaxi_emrr_prog_full
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[14] emaxi_emrr_wr_en
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[13] emrq_rd_en
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[12 esaxi_emrq_prog_full
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[11] esaxi_emrq_wr_en
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[10] emwr_rd_en
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[9] esaxi_emwr_prog_full
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[8] esaxi_emwr_wr_en
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##########Sticky signals below#############
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[7] reserved
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[6] emrr_full (rx)
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[5] emrq_full (rx)
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[4] emwr_full (rx)
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[3] emaxi_emrr_full (tx)
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[2] esaxi_emrq_full (tx)
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[1] esaxi_emwr_full (tx)
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[0] embox_full (mailbox)
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########################################################################
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*/
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module elink(/*AUTOARG*/
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// Outputs
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colid, rowid, chip_resetb, cclk_p, cclk_n, rxo_wr_wait_p,
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@ -33,7 +256,8 @@ module elink(/*AUTOARG*/
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parameter MW = 44;
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parameter INC_PLL = 1; //include pll
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parameter INC_SPI = 1; //include spi block
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parameter ELINKID = 12'h810; //elink ID (used for registers)
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/****************************/
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/*CLK AND RESET */
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/****************************/
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@ -50,7 +274,7 @@ module elink(/*AUTOARG*/
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output [3:0] colid; //epiphany colid
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output [3:0] rowid; //epiphany rowid
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output chip_resetb; //chip reset for Epiphany (active low)
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output cclk_p, cclk_n; //high speed clock (1GHz) to Epiphany
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output cclk_p, cclk_n; //high speed clock (1GHz) to Epiphany
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//Receiver
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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@ -70,8 +294,8 @@ module elink(/*AUTOARG*/
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/*AXI master interface */
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/*****************************/
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//Clock and reset
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input m_axi_aclk;
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input m_axi_aresetn;
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input m_axi_aclk; //axi master clock
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input m_axi_aresetn; //axi master reset (active low)
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//Read address channel
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output [31:0] m_axi_araddr; //read address
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@ -95,19 +319,19 @@ module elink(/*AUTOARG*/
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output [2:0] m_axi_awsize;
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output m_axi_awvalid;
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//Buffered write response channel
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//Write response channel
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output m_axi_bready;
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input [1:0] m_axi_bresp;
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input m_axi_bvalid;
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//Read channel
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//Read data channel
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input [63:0] m_axi_rdata;
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input m_axi_rlast; //indicates last transfer of a burst
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output m_axi_rready; //read ready signal
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input [1:0] m_axi_rresp;
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input m_axi_rvalid;
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//Write channel
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//Write data channel
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output [63:0] m_axi_wdata;
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output m_axi_wlast; //indicates last transfer of a burs
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input m_axi_wready; //response ready
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@ -1,4 +1,3 @@
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module erx_io (/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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@ -1,131 +0,0 @@
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module esaxi_cfg (/*AUTOARG*/
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// Outputs
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s_axi_arready, s_axi_awready, s_axi_bresp, s_axi_bvalid,
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s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_wready, mi_clk,
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mi_en, mi_we, mi_addr, mi_din,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_araddr, s_axi_arprot,
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s_axi_arvalid, s_axi_awaddr, s_axi_awprot, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
mi_rd_data
|
||||
);
|
||||
|
||||
parameter RFAW = 13;
|
||||
|
||||
/*****************************/
|
||||
/*AXI 32 bit lite interface */
|
||||
/*****************************/
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
|
||||
//read address channel
|
||||
input [15:0] s_axi_araddr;
|
||||
input [2:0] s_axi_arprot;
|
||||
output s_axi_arready;
|
||||
input s_axi_arvalid;
|
||||
|
||||
//write address channel
|
||||
input [15:0] s_axi_awaddr;
|
||||
input [2:0] s_axi_awprot;
|
||||
output s_axi_awready;
|
||||
input s_axi_awvalid;
|
||||
|
||||
//buffered read response channel
|
||||
input s_axi_bready;
|
||||
output [1:0] s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
|
||||
//read channel
|
||||
output [31:0] s_axi_rdata;
|
||||
input s_axi_rready;
|
||||
output [1:0] s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
|
||||
//write channel
|
||||
input [31:0] s_axi_wdata;
|
||||
output s_axi_wready;
|
||||
input [3:0] s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
|
||||
/*****************************/
|
||||
/*Simple memory interface */
|
||||
/*****************************/
|
||||
output mi_clk;
|
||||
output mi_en;
|
||||
output [3:0] mi_we;
|
||||
output [15:0] mi_addr;
|
||||
output [31:0] mi_din;
|
||||
input [31:0] mi_rd_data;
|
||||
|
||||
|
||||
`ifdef TARGET_XILINX
|
||||
|
||||
/*axi_bram_ctrl_16b AUTO_TEMPLATE (
|
||||
//Outputs
|
||||
.bram_rst_a (),
|
||||
.bram_clk_a (mi_clk),
|
||||
.bram_en_a (mi_en),
|
||||
.bram_we_a (mi_we[3:0]),
|
||||
.bram_addr_a (mi_addr[15:0]),
|
||||
.bram_wrdata_a (mi_din[31:0]),
|
||||
.bram_rddata_a (mi_rd_data[31:0]),
|
||||
);
|
||||
*/
|
||||
|
||||
axi_bram_ctrl_16b axi_bram_ctrl_16b(/*AUTOINST*/
|
||||
// Outputs
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_wready (s_axi_wready),
|
||||
.s_axi_bresp (s_axi_bresp[1:0]),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_rdata (s_axi_rdata[31:0]),
|
||||
.s_axi_rresp (s_axi_rresp[1:0]),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.bram_rst_a (), // Templated
|
||||
.bram_clk_a (mi_clk), // Templated
|
||||
.bram_en_a (mi_en), // Templated
|
||||
.bram_we_a (mi_we[3:0]), // Templated
|
||||
.bram_addr_a (mi_addr[15:0]), // Templated
|
||||
.bram_wrdata_a (mi_din[31:0]), // Templated
|
||||
// Inputs
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_awaddr (s_axi_awaddr[15:0]),
|
||||
.s_axi_awprot (s_axi_awprot[2:0]),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_wdata (s_axi_wdata[31:0]),
|
||||
.s_axi_wstrb (s_axi_wstrb[3:0]),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_araddr (s_axi_araddr[15:0]),
|
||||
.s_axi_arprot (s_axi_arprot[2:0]),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.bram_rddata_a (mi_rd_data[31:0])); // Templated
|
||||
|
||||
|
||||
`endif // `ifdef TARGET_XILINX
|
||||
|
||||
|
||||
endmodule // esaxi_cfg
|
||||
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../../stubs/hdl")
|
||||
// End:
|
||||
Loading…
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Reference in New Issue
Block a user