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Rallying around TARGET for any platform specific RTL

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aolofsson 2022-06-17 15:10:19 -04:00
parent f0372e5afe
commit 1d7dd09b19
5 changed files with 20 additions and 30 deletions
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8
src/stdlib/hdl/oh_dsync.v
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@ -8,8 +8,7 @@
module oh_dsync
#(parameter SYNCPIPE = 2, // number of sync stages
parameter DELAY = 0, // random delay
parameter SYN = "TRUE", // true=synthesizable
parameter TYPE = "DEFAULT" // scell type/size
parameter TARGET = "DEFAULT" // scell type/size
)
(
input clk, // clock
@ -19,7 +18,7 @@ module oh_dsync
);
generate
if(SYN == "TRUE") begin
if(TARGET == "DEFAULT") begin
reg [SYNCPIPE:0] sync_pipe;
always @ (posedge clk or negedge nreset)
if(!nreset)
@ -32,8 +31,7 @@ module oh_dsync
end // block: reg
else
begin
asic_dsync #(.TYPE(TYPE),
.SYN(SYN),
asic_dsync #(.TARGET(TARGET),
.SYNCPIPE(SYNCPIPE))
asic_dsync (.clk(clk),
.nreset(nreset),

15
src/stdlib/hdl/oh_fifo_async.v
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@ -14,8 +14,7 @@ module oh_fifo_async
parameter REG = 1, // Register fifo output
parameter AW = $clog2(DEPTH),// rd_count width (derived)
parameter SYNCPIPE = 2, // depth of synchronization pipeline
parameter SYN = "TRUE", // synthesizable
parameter TYPE = "DEFAULT", // implementation type
parameter TARGET = "DEFAULT", // implementation type
parameter PROGFULL = DEPTH-1, // programmable almost full level
parameter SHAPE = "SQUARE" // hard macro shape (square, tall, wide)
)
@ -63,19 +62,17 @@ module oh_fifo_async
wire rd_nreset;
wire wr_nreset;
//###########################
//# Reset synchronizers
//###########################
oh_rsync #(.SYN(SYN),
oh_rsync #(.TARGET(TARGET),
.SYNCPIPE(SYNCPIPE))
wr_rsync (.nrst_out (wr_nreset),
.clk (wr_clk),
.nrst_in (nreset));
oh_rsync #(.SYN(SYN),
oh_rsync #(.TARGET(TARGET),
.SYNCPIPE(SYNCPIPE))
rd_rsync (.nrst_out (rd_nreset),
.clk (rd_clk),
@ -116,7 +113,7 @@ module oh_fifo_async
.in (wr_addr[AW:0]));
// synchronize to read clock
oh_dsync #(.SYN(SYN),
oh_dsync #(.TARGET(TARGET),
.SYNCPIPE(SYNCPIPE))
wr_sync[AW:0] (.dout (wr_addr_gray_sync[AW:0]),
.clk (rd_clk),
@ -132,7 +129,7 @@ module oh_fifo_async
.in (rd_addr[AW:0]));
//synchronize to wr clock
oh_dsync #(.SYN(SYN),
oh_dsync #(.TARGET(TARGET),
.SYNCPIPE(SYNCPIPE))
rd_sync[AW:0] (.dout (rd_addr_gray_sync[AW:0]),
.clk (wr_clk),
@ -157,7 +154,7 @@ module oh_fifo_async
oh_memory_dp #(.N(N),
.DEPTH(DEPTH),
.REG(REG),
.SYN(SYN),
.TARGET(TARGET),
.SHAPE(SHAPE))
oh_memory_dp(.wr_wem ({(N){1'b1}}),
.wr_en (fifo_write),

14
src/stdlib/hdl/oh_fifo_cdc.v
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@ -6,11 +6,10 @@
//#############################################################################
module oh_fifo_cdc
#(parameter N = 32, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter SYN = "TRUE", // true=synthesizable
parameter TYPE = "DEFAULT", // true=synthesizable
parameter AW = $clog2(DEPTH) // rd_count width (derived)
#(parameter N = 32, // fifo width
parameter DEPTH = 32, // fifo depth
parameter TARGET = "DEFAULT", // synthesis/sim target
parameter AW = $clog2(DEPTH) // rd_count width (derived)
)
(
input nreset, // async active low reset
@ -36,8 +35,7 @@ module oh_fifo_cdc
assign ready_out = ~(wr_almost_full | wr_full | wr_prog_full);
//async asser, sync deassert of reset
oh_rsync #(.SYN(SYN),
.TYPE(TYPE))
oh_rsync #(.TARGET(TARGET))
sync_reset(.nrst_out (nreset_out),
.clk (clk_out),
.nrst_in (nreset));
@ -50,7 +48,7 @@ module oh_fifo_cdc
valid_out <= rd_en;
// parametric async fifo
oh_fifo_async #(.SYN(SYN),
oh_fifo_async #(.TARGET(TARGET),
.N(N),
.DEPTH(DEPTH))
oh_fifo_async (

5
src/stdlib/hdl/oh_memory_dp.v
View File

@ -9,8 +9,7 @@ module oh_memory_dp
#(parameter N = 32, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output
parameter SYN = "TRUE", // hard (macro) or soft (rtl)
parameter TYPE = "DEFAULT", // pass through variable for hard macro
parameter TARGET = "DEFAULT", // pass through variable for hard macro
parameter SHAPE = "SQUARE", // hard macro shape (square, tall, wide)
parameter AW = $clog2(DEPTH) // rd_count width (derived)
)
@ -40,7 +39,7 @@ module oh_memory_dp
);
generate
if(SYN == "TRUE") begin
if(TARGET == "DEFAULT") begin
//#########################################
// Generic RAM for synthesis
//#########################################

8
src/stdlib/hdl/oh_rsync.v
View File

@ -7,8 +7,7 @@
module oh_rsync
#(parameter SYNCPIPE = 2, // number of sync stages
parameter SYN = "TRUE", // true=synthesizable
parameter TYPE = "DEFAULT" // scell type/size
parameter TARGET = "DEFAULT" // scell type/size
)
(
input clk,
@ -17,7 +16,7 @@ module oh_rsync
);
generate
if(SYN == "TRUE")
if(TARGET == "DEFAULT")
begin
reg [SYNCPIPE-1:0] sync_pipe;
always @ (posedge clk or negedge nrst_in)
@ -29,8 +28,7 @@ module oh_rsync
end
else
begin
asic_rsync #(.TYPE(TYPE),
.SYN(SYN),
asic_rsync #(.TARGET(TARGET),
.SYNCPIPE(SYNCPIPE))
asic_rsync (.clk(clk),
.nrst_in(nrst_in),