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Fixing burst transmit bug

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- The burst should be interrupted as soon as there is a wait signal. When the wait stops, a new frame naturally starts.
This commit is contained in:
Andreas Olofsson 2015-11-11 22:33:54 -05:00
parent fa5011937c
commit 1dcd9a82bd
2 changed files with 19 additions and 20 deletions
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5
elink/hdl/etx_io.v
View File

@ -42,9 +42,7 @@ module etx_io (/*AUTOARG*/
//############
reg [7:0] tx_pointer;
reg [15:0] tx_data16;
reg tx_access_reg;
reg tx_frame;
reg tx_io_wait_reg;
reg [PW-1:0] tx_packet_reg;
reg [63:0] tx_double;
reg [2:0] tx_state_reg;
@ -97,7 +95,6 @@ always @ (posedge tx_lclk_io)
assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
//Creating wide acknowledge on cycle 4
always @ (posedge tx_lclk_io)
if(!nreset)
@ -130,7 +127,6 @@ always @ (posedge tx_lclk_io)
.srcaddr_out (srcaddr[31:0]),
.packet_in (tx_packet_reg[PW-1:0]));
/*
* The following format is used by the Epiphany multicore ASIC.
* Don't change it if you want to communicate with Epiphany.
@ -274,6 +270,7 @@ always @ (posedge tx_lclk_io)
//On Parallella this signal comes in single-ended
assign tx_rd_wait = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:

34
elink/hdl/etx_protocol.v
View File

@ -41,10 +41,10 @@ module etx_protocol (/*AUTOARG*/
//###################################################################
//# Local regs & wires
//###################################################################
reg tx_burst;
reg tx_burst;
reg tx_access;
reg [PW-1:0] tx_packet;
wire tx_rd_wait_sync;
wire tx_wr_wait_sync;
wire etx_write;
@ -61,7 +61,8 @@ module etx_protocol (/*AUTOARG*/
wire burst_type_match;
wire [31:0] burst_addr;
wire burst_addr_match;
wire burst_in;
//packet to emesh bundle
packet2emesh p2m0 (
.write_out (etx_write),
@ -92,9 +93,9 @@ module etx_protocol (/*AUTOARG*/
else if (tx_io_ack)
tx_io_wait <= 1'b0;
else if (tx_access & ~tx_burst)
tx_io_wait <= 1'b1;
tx_io_wait <= ~burst_in;
//Prepare transaction / with burst
//Hold transaction while waiting
always @ (posedge clk)
if(!nreset)
begin
@ -106,20 +107,15 @@ module etx_protocol (/*AUTOARG*/
tx_packet[PW-1:0] <= etx_packet[PW-1:0];
tx_access <= etx_valid;
end
always @ (posedge clk)
if(!nreset)
tx_burst <= 1'b0;
else
tx_burst <= (etx_write & //write
(etx_datamode[1:0]==2'b11) & //double only
burst_type_match & //same types
burst_addr_match); //inc by 8
//#############################
//# Burst Detection
//#############################
always @ (posedge clk)
if(!nreset)
tx_burst <= 1'b0;
else
tx_burst <= burst_in;
packet2emesh p2m1 (
.write_out (last_write),
@ -137,8 +133,14 @@ module etx_protocol (/*AUTOARG*/
assign burst_type_match = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
==
{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
assign burst_in = ~tx_wr_wait_sync & //interrupt burst on wait
etx_write & //write
(etx_datamode[1:0]==2'b11) & //double only
burst_type_match & //same types
burst_addr_match; //inc by 8
//#############################
//# Wait signals (async)
//#############################