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https://github.com/aolofsson/oh.git
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Splitting register file (rx,tx,base)
The goal is to have 100% independence in RX and TX pipes
This commit is contained in:
Andreas Olofsson
parent
0d10fbd26f
commit
1e1644138e
142
elink/hdl/ecfg_if.v
Normal file
142
elink/hdl/ecfg_if.v
Normal file
@ -0,0 +1,142 @@
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/*
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########################################################################
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ELINK CONFIGURATION INTERFACE
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########################################################################
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*/
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module ecfg_if (/*AUTOARG*/
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// Outputs
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rxrr_access, rxrr_packet, mi_clk, mi_en, mi_we, mi_addr, mi_din,
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// Inputs
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txwr_clk, txwr_access, txwr_packet, txrd_access, txrd_packet,
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rxrr_clk, mi_ba_cfg_dout, mi_rx_cfg_dout, mi_rx_edma_dout,
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mi_rx_emmu_dout, mi_rx_mailbox_dout, mi_tx_cfg_dout,
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mi_tx_emmu_dout
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);
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parameter [11:0] ELINKID = 12'h810;
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parameter DW = 32;
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parameter AW = 32;
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parameter PW = 104;
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/******************************/
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/*Host Write Interface */
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/******************************/
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input txwr_clk; //write clock used as mi_clk
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input txwr_access;
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input [PW-1:0] txwr_packet;
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/******************************/
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/*Host Write Interface */
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/******************************/
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input txrd_access;
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input [PW-1:0] txrd_packet;
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/******************************/
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/*Host Write Interface */
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/******************************/
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input rxrr_clk;
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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/******************************/
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/*Register Interface */
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/******************************/
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output mi_clk;
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output mi_en;
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output mi_we;
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output [19:0] mi_addr;
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output [31:0] mi_din;
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/******************************/
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/*Readback Data */
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/******************************/
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//base
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input [31:0] mi_ba_cfg_dout;
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//rx
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input [DW-1:0] mi_rx_cfg_dout;
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input [DW-1:0] mi_rx_edma_dout;
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input [DW-1:0] mi_rx_emmu_dout;
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input [DW-1:0] mi_rx_mailbox_dout;
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//tx
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input [DW-1:0] mi_tx_cfg_dout;
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input [DW-1:0] mi_tx_emmu_dout;
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//wires
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wire [DW-1:0] txwr_data;
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wire [AW-1:0] txwr_dstaddr;
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wire [AW-1:0] txwr_srcaddr;
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wire [AW-1:0] txrd_dstaddr;
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wire [AW-1:0] txrd_srcaddr;
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wire mi_wr;
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wire mi_rd;
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//splicing packets
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packet2emesh p2e_wr(.access_out (),
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.write_out (),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (txwr_dstaddr[AW-1:0]),
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.data_out (txwr_data[DW-1:0]),
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.srcaddr_out (),
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.packet_in (txwr_packet[PW-1:0])
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);
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packet2emesh p2e_rd(.access_out (),
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.write_out (),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (txrd_dstaddr[AW-1:0]),
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.data_out (),
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.srcaddr_out (txrd_srcaddr[AW-1:0]),
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.packet_in (txrd_packet[PW-1:0])
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);
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//pass through clock
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//TODO: gate?
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assign mi_clk = txwr_clk;
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//Register file access (from slave)
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assign mi_wr = txwr_access & (txwr_dstaddr[31:20]==ELINKID);
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assign mi_rd = txrd_access & (txrd_dstaddr[31:20]==ELINKID);
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//Only 32 bit writes supported
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assign mi_we = mi_wr;
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assign mi_en = mi_wr | mi_rd;
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//Read/write address
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assign mi_addr[19:0] = mi_we ? txwr_dstaddr[19:0] :
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txrd_dstaddr[19:0];
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//Data
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assign mi_din[31:0] = txwr_data[31:0];
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//TODO: Do readback later....
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endmodule // ecfg_base
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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130
elink/hdl/ecfg_rx.v
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130
elink/hdl/ecfg_rx.v
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@ -0,0 +1,130 @@
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/*
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########################################################################
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ELINK CONFIGURATION REGISTER FILE
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########################################################################
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*/
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module ecfg_rx (/*AUTOARG*/
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// Outputs
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mi_dout, ecfg_rx_enable, ecfg_rx_mmu_enable,
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// Inputs
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reset, mi_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_rx_datain,
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ecfg_rx_debug
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);
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/******************************/
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/*Compile Time Parameters */
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/******************************/
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parameter RFAW = 5; // 32 registers for now
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/******************************/
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/*HARDWARE RESET (EXTERNAL) */
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/******************************/
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input reset; // ecfg registers reset only by "hard reset"
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input mi_clk;
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input mi_en;
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input mi_we; // single we, must write 32 bit words
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input [19:0] mi_addr; // complete physical address (no shifting!)
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*CONFIG SIGNALS */
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/*****************************/
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//rx
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output ecfg_rx_enable; // enable signal for rx
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output ecfg_rx_mmu_enable; // enables MMU on rx path
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input [8:0] ecfg_rx_datain; // frame and data inputs
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input [15:0] ecfg_rx_debug; // erx debug signals
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg [4:0] ecfg_rx_reg;
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reg [8:0] ecfg_datain_reg;
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reg [8:0] ecfg_datain_sync;
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reg [2:0] ecfg_rx_debug_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_rx_write;
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRX);
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//###########################
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//# RXCFG
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_rx_reg[4:0] <= 5'b0;
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else if (ecfg_rx_write)
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ecfg_rx_reg[4:0] <= mi_din[4:0];
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assign ecfg_rx_enable = ecfg_rx_reg[0];
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assign ecfg_rx_mmu_enable = ecfg_rx_reg[1];
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//###########################
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//# DATAIN (synchronized)
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//###########################
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always @ (posedge mi_clk)
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begin
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ecfg_datain_sync[8:0] <= ecfg_rx_datain[8:0];
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ecfg_datain_reg[8:0] <= ecfg_datain_sync[8:0];
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end
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//###########################1
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//# DEBUG
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_rx_debug_reg[2:0] <= 'd0;
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else
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ecfg_rx_debug_reg[2:0] <=ecfg_rx_debug_reg[2:0] | ecfg_rx_debug[2:0];
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge mi_clk)
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if(ecfg_read)
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case(mi_addr[RFAW+1:2])
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`ELRX: mi_dout[31:0] <= {27'b0, ecfg_rx_reg[4:0]};
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`ELDATAIN: mi_dout[31:0] <= {23'b0, ecfg_datain_reg[8:0]};
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default: mi_dout[31:0] <= 32'd0;
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endcase
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endmodule // ecfg
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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||||
(at your option) any later version.This program is distributed in the hope
|
||||
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
|
||||
of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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144
elink/hdl/ecfg_tx.v
Normal file
144
elink/hdl/ecfg_tx.v
Normal file
@ -0,0 +1,144 @@
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/*
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########################################################################
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ELINK CONFIGURATION REGISTER FILE
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########################################################################
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*/
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module ecfg_tx (/*AUTOARG*/
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// Outputs
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mi_dout, ecfg_tx_enable, ecfg_tx_mmu_enable, ecfg_tx_gpio_enable,
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ecfg_tx_ctrlmode, ecfg_tx_ctrlmode_bp, ecfg_dataout,
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// Inputs
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reset, mi_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_tx_debug
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);
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/******************************/
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/*Compile Time Parameters */
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/******************************/
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parameter RFAW = 5; // 32 registers for now
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parameter DEFAULT_COREID = 12'h808; // reset value for ecfg_coreid
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parameter DEFAULT_VERSION = 16'h0000; // reset value for version
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parameter DEFAULT_CLKDIV = 4'd7;
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/******************************/
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/*HARDWARE RESET (EXTERNAL) */
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/******************************/
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input reset; // ecfg registers reset only by "hard reset"
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input mi_clk;
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input mi_en;
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input mi_we; // single we, must write 32 bit words
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input [19:0] mi_addr; // complete physical address (no shifting!)
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*ELINK CONTROL SIGNALS */
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/*****************************/
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//tx
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output ecfg_tx_enable; // enable signal for TX
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output ecfg_tx_mmu_enable; // enables MMU on transmit path
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output ecfg_tx_gpio_enable; // forces TX output pins to constants
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output [3:0] ecfg_tx_ctrlmode; // value for emesh ctrlmode tag
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output ecfg_tx_ctrlmode_bp; // bypass value for emesh ctrlmode tag
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output [8:0] ecfg_dataout; // data for elink outputs
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input [15:0] ecfg_tx_debug; // etx debug signals
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg [8:0] ecfg_tx_reg;
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reg [8:0] ecfg_dataout_reg;
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reg [2:0] ecfg_tx_debug_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_tx_write;
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wire ecfg_dataout_write;
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_tx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTX);
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assign ecfg_dataout_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELDATAOUT);
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//###########################
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//# TX
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_tx_reg[8:0] <= 9'b0;
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else if (ecfg_tx_write)
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ecfg_tx_reg[8:0] <= mi_din[8:0];
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assign ecfg_tx_enable = ecfg_tx_reg[0];
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assign ecfg_tx_mmu_enable = ecfg_tx_reg[1];
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assign ecfg_tx_gpio_enable = (ecfg_tx_reg[3:2]==2'b01);
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assign ecfg_tx_tp_enable = (ecfg_tx_reg[3:2]==2'b10);//test clock pattern
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assign ecfg_tx_ctrlmode[3:0] = ecfg_tx_reg[7:4];
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assign ecfg_tx_ctrlmode_bp = ecfg_tx_reg[8];
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//###########################
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//# DATAOUT
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_dataout_reg[8:0] <= 'd0;
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else if (ecfg_dataout_write)
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ecfg_dataout_reg[8:0] <= mi_din[8:0];
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assign ecfg_dataout[8:0] = ecfg_dataout_reg[8:0];
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//###########################1
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//# DEBUG
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_tx_debug_reg[2:0] <= 'd0;
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else
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ecfg_tx_debug_reg[2:0] <=ecfg_tx_debug_reg[2:0] | ecfg_tx_debug[2:0];
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge mi_clk)
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if(ecfg_read)
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case(mi_addr[RFAW+1:2])
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`ELTX: mi_dout[31:0] <= {23'b0, ecfg_tx_reg[8:0]};
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`ELDATAOUT: mi_dout[31:0] <= {23'b0, ecfg_dataout_reg[8:0]};
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`ELDEBUG: mi_dout[31:0] <= {16'b0,ecfg_tx_debug[15:3],ecfg_tx_debug_reg[2:0]};
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default: mi_dout[31:0] <= 32'd0;
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endcase
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endmodule // ecfg_tx
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.This program is distributed in the hope
|
||||
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details. You should have received a copy
|
||||
of the GNU General Public License along with this program (see the file
|
||||
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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