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-dma with packet format
-using the fifo_cdc block
This commit is contained in:
Andreas Olofsson 2015-05-03 23:29:32 -04:00
parent 51b14f41ce
commit 1ee720fc67
5 changed files with 254 additions and 249 deletions
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4
elink/hdl/ecfg_if.v
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@ -30,8 +30,8 @@ module ecfg_if (/*AUTOARG*/
/********************************/ /********************************/
input access_in; input access_in;
input [PW-1:0] packet_in; input [PW-1:0] packet_in;
output wait_out; //outgoing wait output wait_out;
/********************************/ /********************************/
/* Register Interface */ /* Register Interface */
/********************************/ /********************************/

2
elink/hdl/ecfg_tx.v
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@ -99,7 +99,7 @@ module ecfg_tx (/*AUTOARG*/
else if (ecfg_tx_config_write) else if (ecfg_tx_config_write)
ecfg_tx_config_reg[10:0] <= mi_din[10:0]; ecfg_tx_config_reg[10:0] <= mi_din[10:0];
assign tx_enable = ecfg_tx_config_reg[0]; assign tx_enable = 1'b1;//TODO: fix! ecfg_tx_config_reg[0];
assign mmu_enable = ecfg_tx_config_reg[1]; assign mmu_enable = ecfg_tx_config_reg[1];
assign remap_enable = ecfg_tx_config_reg[3:2]==2'b01; assign remap_enable = ecfg_tx_config_reg[3:2]==2'b01;
assign ctrlmode[3:0] = ecfg_tx_config_reg[7:4]; assign ctrlmode[3:0] = ecfg_tx_config_reg[7:4];

5
elink/hdl/eclocks.v
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@ -58,7 +58,7 @@ module eclocks (/*AUTOARG*/
.clkout (cclk), .clkout (cclk),
.clkout90 (), .clkout90 (),
// Inputs // Inputs
.clkin (clkin & cclk_en), .clkin (clkin),
.reset (hard_reset), .reset (hard_reset),
.divcfg (ecfg_clk_settings[7:4]) .divcfg (ecfg_clk_settings[7:4])
); );
@ -68,7 +68,7 @@ module eclocks (/*AUTOARG*/
.clkout (tx_lclk), .clkout (tx_lclk),
.clkout90 (tx_lclk90), .clkout90 (tx_lclk90),
// Inputs // Inputs
.clkin (clkin & lclk_en), .clkin (clkin),
.reset (hard_reset), .reset (hard_reset),
.divcfg (ecfg_clk_settings[11:8]) .divcfg (ecfg_clk_settings[11:8])
); );
@ -86,6 +86,7 @@ module eclocks (/*AUTOARG*/
//Output buffer //Output buffer
//Keep clocks on at all times
assign cclk_p = cclk & cclk_en ; assign cclk_p = cclk & cclk_en ;
assign cclk_n = ~cclk_p; assign cclk_n = ~cclk_p;

162
elink/hdl/erx.v
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@ -59,34 +59,34 @@ module erx (/*AUTOARG*/
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire edma_access; // From edma of edma.v wire edma_access; // From erx_dma of edma.v
wire edma_wait; // From erx_disty of erx_disty.v wire edma_wait; // From erx_disty of erx_disty.v
wire emesh_remap_access; // From erx_remap of erx_remap.v wire emesh_remap_access; // From erx_remap of erx_remap.v
wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v
wire emmu_access; // From emmu of emmu.v wire emmu_access; // From erx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From emmu of emmu.v wire [PW-1:0] emmu_packet; // From erx_mmu of emmu.v
wire erx_access; // From erx_protocol of erx_protocol.v wire erx_access; // From erx_protocol of erx_protocol.v
wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
wire erx_wait; // From erx_disty of erx_disty.v wire erx_wait; // From erx_disty of erx_disty.v
wire [8:0] gpio_datain; // From erx_io of erx_io.v wire [8:0] gpio_datain; // From erx_io of erx_io.v
wire [14:0] mi_addr; // From ecfg_if of ecfg_if.v wire [14:0] mi_addr; // From erx_cfgif of ecfg_if.v
wire [DW-1:0] mi_cfg_dout; // From ecfg_rx of ecfg_rx.v wire [DW-1:0] mi_cfg_dout; // From erx_cfg of ecfg_rx.v
wire mi_cfg_en; // From ecfg_if of ecfg_if.v wire mi_cfg_en; // From erx_cfgif of ecfg_if.v
wire [63:0] mi_din; // From ecfg_if of ecfg_if.v wire [63:0] mi_din; // From erx_cfgif of ecfg_if.v
wire [DW-1:0] mi_dma_dout; // From edma of edma.v wire [DW-1:0] mi_dma_dout; // From erx_dma of edma.v
wire mi_dma_en; // From ecfg_if of ecfg_if.v wire mi_dma_en; // From erx_cfgif of ecfg_if.v
wire [31:0] mi_mailbox_dout; // From emailbox of emailbox.v wire [31:0] mi_mailbox_dout; // From erx_mailbox of emailbox.v
wire [DW-1:0] mi_mmu_dout; // From emmu of emmu.v wire [DW-1:0] mi_mmu_dout; // From erx_mmu of emmu.v
wire mi_mmu_en; // From ecfg_if of ecfg_if.v wire mi_mmu_en; // From erx_cfgif of ecfg_if.v
wire mi_we; // From ecfg_if of ecfg_if.v wire mi_we; // From erx_cfgif of ecfg_if.v
wire mmu_enable; // From ecfg_rx of ecfg_rx.v wire mmu_enable; // From erx_cfg of ecfg_rx.v
wire [31:0] remap_base; // From ecfg_rx of ecfg_rx.v wire [31:0] remap_base; // From erx_cfg of ecfg_rx.v
wire remap_bypass; // From erx_protocol of erx_protocol.v wire remap_bypass; // From erx_protocol of erx_protocol.v
wire [1:0] remap_mode; // From ecfg_rx of ecfg_rx.v wire [1:0] remap_mode; // From erx_cfg of ecfg_rx.v
wire [11:0] remap_pattern; // From ecfg_rx of ecfg_rx.v wire [11:0] remap_pattern; // From erx_cfg of ecfg_rx.v
wire [11:0] remap_sel; // From ecfg_rx of ecfg_rx.v wire [11:0] remap_sel; // From erx_cfg of ecfg_rx.v
wire [63:0] rx_data_par; // From erx_io of erx_io.v wire [63:0] rx_data_par; // From erx_io of erx_io.v
wire rx_enable; // From ecfg_rx of ecfg_rx.v wire rx_enable; // From erx_cfg of ecfg_rx.v
wire [7:0] rx_frame_par; // From erx_io of erx_io.v wire [7:0] rx_frame_par; // From erx_io of erx_io.v
wire rx_rd_wait; // From erx_disty of erx_disty.v wire rx_rd_wait; // From erx_disty of erx_disty.v
wire rx_wr_wait; // From erx_disty of erx_disty.v wire rx_wr_wait; // From erx_disty of erx_disty.v
@ -196,7 +196,8 @@ module erx (/*AUTOARG*/
//Inputs //Inputs
.emesh_\(.*\)_in (emesh_remap_\1[]), .emesh_\(.*\)_in (emesh_remap_\1[]),
.mmu_en (mmu_enable), .mmu_en (mmu_enable),
.clk (rx_lclk_div4), .rd_clk (rx_lclk_div4),
.wr_clk (rx_lclk_div4),
.mi_dout (mi_mmu_dout[DW-1:0]), .mi_dout (mi_mmu_dout[DW-1:0]),
.emesh_packet_hi_out (), .emesh_packet_hi_out (),
.mmu_bp (remap_bypass), .mmu_bp (remap_bypass),
@ -207,23 +208,24 @@ module erx (/*AUTOARG*/
emmu erx_mmu ( emmu erx_mmu (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated .mi_dout (mi_mmu_dout[DW-1:0]), // Templated
.emesh_access_out (emmu_access), // Templated .emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated .emesh_packet_out (emmu_packet[PW-1:0]), // Templated
.emesh_packet_hi_out (), // Templated .emesh_packet_hi_out (), // Templated
// Inputs // Inputs
.reset (reset), .reset (reset),
.clk (rx_lclk_div4), // Templated .rd_clk (rx_lclk_div4), // Templated
.mmu_en (mmu_enable), // Templated .wr_clk (rx_lclk_div4), // Templated
.mmu_bp (remap_bypass), // Templated .mmu_en (mmu_enable), // Templated
.mi_en (mi_mmu_en), // Templated .mmu_bp (remap_bypass), // Templated
.mi_we (mi_we), .mi_en (mi_mmu_en), // Templated
.mi_addr (mi_addr[14:0]), .mi_we (mi_we),
.mi_din (mi_din[DW-1:0]), .mi_addr (mi_addr[14:0]),
.emesh_access_in (emesh_remap_access), // Templated .mi_din (mi_din[DW-1:0]),
.emesh_packet_in (emesh_remap_packet[PW-1:0]), // Templated .emesh_access_in (emesh_remap_access), // Templated
.emesh_wait_in (erx_wait)); // Templated .emesh_packet_in (emesh_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (erx_wait)); // Templated
@ -243,26 +245,26 @@ module erx (/*AUTOARG*/
defparam erx_cfgif.RX=1; defparam erx_cfgif.RX=1;
ecfg_if erx_cfgif (/*AUTOINST*/ ecfg_if erx_cfgif (/*AUTOINST*/
// Outputs // Outputs
.wait_out (), // Templated .wait_out (), // Templated
.mi_mmu_en (mi_mmu_en), .mi_mmu_en (mi_mmu_en),
.mi_dma_en (mi_dma_en), .mi_dma_en (mi_dma_en),
.mi_cfg_en (mi_cfg_en), .mi_cfg_en (mi_cfg_en),
.mi_we (mi_we), .mi_we (mi_we),
.mi_addr (mi_addr[14:0]), .mi_addr (mi_addr[14:0]),
.mi_din (mi_din[63:0]), .mi_din (mi_din[63:0]),
.access_out (), // Templated .access_out (), // Templated
.packet_out (), // Templated .packet_out (), // Templated
// Inputs // Inputs
.clk (rx_lclk_div4), // Templated .clk (rx_lclk_div4), // Templated
.reset (reset), .reset (reset),
.access_in (erx_cfg_access), // Templated .access_in (erx_cfg_access), // Templated
.packet_in (erx_cfg_packet[PW-1:0]), // Templated .packet_in (erx_cfg_packet[PW-1:0]), // Templated
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated .mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated .mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated .mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
.mi_dout3 (mi_mailbox_dout[63:0]), // Templated .mi_dout3 (mi_mailbox_dout[63:0]), // Templated
.wait_in (erx_cfg_wait)); // Templated .wait_in (erx_cfg_wait)); // Templated
/************************************************************/ /************************************************************/
@ -331,17 +333,17 @@ module erx (/*AUTOARG*/
//shares register space with ecfg_rx //shares register space with ecfg_rx
emailbox erx_mailbox(.mi_en (mi_cfg_en), emailbox erx_mailbox(.mi_en (mi_cfg_en),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_mailbox_dout[31:0]), // Templated .mi_dout (mi_mailbox_dout[31:0]), // Templated
.mailbox_full (mailbox_full), .mailbox_full (mailbox_full),
.mailbox_not_empty (mailbox_not_empty), .mailbox_not_empty(mailbox_not_empty),
// Inputs // Inputs
.reset (reset), .reset (reset),
.wr_clk (rx_lclk_div4), // Templated .wr_clk (rx_lclk_div4), // Templated
.rd_clk (rx_lclk_div4), // Templated .rd_clk (rx_lclk_div4), // Templated
.mi_we (mi_we), .mi_we (mi_we),
.mi_addr (mi_addr[19:0]), .mi_addr (mi_addr[19:0]),
.mi_din (mi_din[63:0])); .mi_din (mi_din[63:0]));
/************************************************************/ /************************************************************/
@ -356,18 +358,18 @@ module erx (/*AUTOARG*/
); );
*/ */
edma erx_dma(/*AUTOINST*/ edma erx_dma(/*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_dma_dout[DW-1:0]), // Templated .mi_dout (mi_dma_dout[DW-1:0]), // Templated
.edma_access (edma_access), // Templated .edma_access (edma_access), // Templated
.edma_packet (edma_packet[PW-1:0]), .edma_packet (edma_packet[PW-1:0]),
// Inputs // Inputs
.reset (reset), .reset (reset),
.clk (rx_lclk_div4), // Templated .clk (rx_lclk_div4), // Templated
.mi_en (mi_dma_en), // Templated .mi_en (mi_dma_en), // Templated
.mi_we (mi_we), .mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]), .mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[63:0]), .mi_din (mi_din[63:0]),
.edma_wait (edma_wait)); .edma_wait (edma_wait));

330
elink/hdl/etx.v
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@ -53,25 +53,28 @@ module etx(/*AUTOARG*/
input etx_cfg_wait; input etx_cfg_wait;
//debug declarations //for status?
wire[15:0] tx_status; wire[15:0] tx_status;
wire txwr_fifo_full;//todo-fix wire txwr_fifo_full;
wire txrr_fifo_full; wire txrr_fifo_full;
wire txrd_fifo_full; wire txrd_fifo_full;
wire txrd_fifo_empty;
wire txrr_fifo_empty;
wire txwr_fifo_empty;
/*AUTOOUTPUT*/ /*AUTOOUTPUT*/
/*AUTOINPUT*/ /*AUTOINPUT*/
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ctrlmode; // From ecfg_tx of ecfg_tx.v wire [3:0] ctrlmode; // From etx_cfg of ecfg_tx.v
wire ctrlmode_bypass; // From ecfg_tx of ecfg_tx.v wire ctrlmode_bypass; // From etx_cfg of ecfg_tx.v
wire edma_access; // From edma of edma.v wire edma_access; // From etx_dma of edma.v
wire [PW-1:0] edma_packet; // From edma of edma.v wire [PW-1:0] edma_packet; // From etx_dma of edma.v
wire edma_wait; // From etx_arbiter of etx_arbiter.v wire edma_wait; // From etx_arbiter of etx_arbiter.v
wire emmu_access; // From emmu of emmu.v wire emmu_access; // From etx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From emmu of emmu.v wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
wire etx_access; // From etx_arbiter of etx_arbiter.v wire etx_access; // From etx_arbiter of etx_arbiter.v
wire etx_io_wait; // From etx_protocol of etx_protocol.v wire etx_io_wait; // From etx_protocol of etx_protocol.v
wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
@ -81,34 +84,34 @@ module etx(/*AUTOARG*/
wire etx_rr; // From etx_arbiter of etx_arbiter.v wire etx_rr; // From etx_arbiter of etx_arbiter.v
wire etx_wait; // From etx_protocol of etx_protocol.v wire etx_wait; // From etx_protocol of etx_protocol.v
wire etx_wr_wait; // From etx_protocol of etx_protocol.v wire etx_wr_wait; // From etx_protocol of etx_protocol.v
wire [8:0] gpio_data; // From ecfg_tx of ecfg_tx.v wire [8:0] gpio_data; // From etx_cfg of ecfg_tx.v
wire gpio_enable; // From ecfg_tx of ecfg_tx.v wire gpio_enable; // From etx_cfg of ecfg_tx.v
wire [14:0] mi_addr; // From ecfg_if of ecfg_if.v wire [14:0] mi_addr; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_cfg_dout; // From ecfg_tx of ecfg_tx.v wire [DW-1:0] mi_cfg_dout; // From etx_cfg of ecfg_tx.v
wire mi_cfg_en; // From ecfg_if of ecfg_if.v wire mi_cfg_en; // From etx_cfgif of ecfg_if.v
wire [63:0] mi_din; // From ecfg_if of ecfg_if.v wire [63:0] mi_din; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_dma_dout; // From edma of edma.v wire [DW-1:0] mi_dma_dout; // From etx_dma of edma.v
wire mi_dma_en; // From ecfg_if of ecfg_if.v wire mi_dma_en; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_mmu_dout; // From emmu of emmu.v wire [DW-1:0] mi_mmu_dout; // From etx_mmu of emmu.v
wire mi_mmu_en; // From ecfg_if of ecfg_if.v wire mi_mmu_en; // From etx_cfgif of ecfg_if.v
wire mi_we; // From ecfg_if of ecfg_if.v wire mi_we; // From etx_cfgif of ecfg_if.v
wire mmu_enable; // From ecfg_tx of ecfg_tx.v wire mmu_enable; // From etx_cfg of ecfg_tx.v
wire remap_enable; // From ecfg_tx of ecfg_tx.v wire remap_enable; // From etx_cfg of ecfg_tx.v
wire tp_enable; // From ecfg_tx of ecfg_tx.v wire tp_enable; // From etx_cfg of ecfg_tx.v
wire [63:0] tx_data_par; // From etx_protocol of etx_protocol.v wire [63:0] tx_data_par; // From etx_protocol of etx_protocol.v
wire tx_enable; // From ecfg_tx of ecfg_tx.v wire tx_enable; // From etx_cfg of ecfg_tx.v
wire [7:0] tx_frame_par; // From etx_protocol of etx_protocol.v wire [7:0] tx_frame_par; // From etx_protocol of etx_protocol.v
wire tx_rd_wait; // From etx_io of etx_io.v wire tx_rd_wait; // From etx_io of etx_io.v
wire tx_wr_wait; // From etx_io of etx_io.v wire tx_wr_wait; // From etx_io of etx_io.v
wire txrd_fifo_empty; // From txrd_fifo of fifo_async.v wire txrd_fifo_access; // From txrd_fifo of fifo_cdc.v
wire [PW-1:0] txrd_fifo_packet; // From txrd_fifo of fifo_async.v wire [PW-1:0] txrd_fifo_packet; // From txrd_fifo of fifo_cdc.v
wire txrd_fifo_read; // From etx_arbiter of etx_arbiter.v wire txrd_fifo_wait; // From etx_arbiter of etx_arbiter.v
wire txrr_fifo_empty; // From txrr_fifo of fifo_async.v wire txrr_fifo_access; // From txrr_fifo of fifo_cdc.v
wire [PW-1:0] txrr_fifo_packet; // From txrr_fifo of fifo_async.v wire [PW-1:0] txrr_fifo_packet; // From txrr_fifo of fifo_cdc.v
wire txrr_fifo_read; // From etx_arbiter of etx_arbiter.v wire txrr_fifo_wait; // From etx_arbiter of etx_arbiter.v
wire txwr_fifo_empty; // From txwr_fifo of fifo_async.v wire txwr_fifo_access; // From txwr_fifo of fifo_cdc.v
wire [PW-1:0] txwr_fifo_packet; // From txwr_fifo of fifo_async.v wire [PW-1:0] txwr_fifo_packet; // From txwr_fifo of fifo_cdc.v
wire txwr_fifo_read; // From etx_arbiter of etx_arbiter.v wire txwr_fifo_wait; // From etx_arbiter of etx_arbiter.v
// End of automatics // End of automatics
wire [15:0] ecfg_status; // To ecfg_tx of ecfg_tx.v wire [15:0] ecfg_status; // To ecfg_tx of ecfg_tx.v
@ -117,77 +120,68 @@ module etx(/*AUTOARG*/
/************************************************************/ /************************************************************/
//TODO: Minimize depth and width //TODO: Minimize depth and width
/*fifo_async AUTO_TEMPLATE ( /*fifo_cdc AUTO_TEMPLATE (
// Outputs // Outputs
.valid (),//TODO: Use?? .access_out (@"(substring vl-cell-name 0 4)"_fifo_access),
.dout (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]), .packet_out (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
.empty (@"(substring vl-cell-name 0 4)"_fifo_empty), .wait_out (@"(substring vl-cell-name 0 4)"_wait),
.full (@"(substring vl-cell-name 0 4)"_wait), .wait_in (@"(substring vl-cell-name 0 4)"_fifo_wait),
.prog_full (), .clk_out (tx_lclk_div4),
// Inputs .clk_in (sys_clk),
.rd_clk (tx_lclk_div4), .access_in (@"(substring vl-cell-name 0 4)"_access),
.wr_clk (sys_clk),
.wr_en (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read), .rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.reset (reset), .reset (reset),
.din (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]), .packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
); );
*/ */
//Write fifo (from slave) //Write fifo (from slave)
fifo_async #(.DW(104), .AW(5)) txwr_fifo( fifo_cdc #(.DW(104), .AW(5)) txwr_fifo(
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.full (txwr_wait), // Templated .wait_out (txwr_wait), // Templated
.prog_full (), // Templated .access_out (txwr_fifo_access), // Templated
.dout (txwr_fifo_packet[PW-1:0]), // Templated .packet_out (txwr_fifo_packet[PW-1:0]), // Templated
.empty (txwr_fifo_empty), // Templated // Inputs
.valid (), // Templated .clk_in (sys_clk), // Templated
// Inputs .clk_out (tx_lclk_div4), // Templated
.reset (reset), // Templated .reset (reset), // Templated
.wr_clk (sys_clk), // Templated .access_in (txwr_access), // Templated
.rd_clk (tx_lclk_div4), // Templated .packet_in (txwr_packet[PW-1:0]), // Templated
.wr_en (txwr_access), // Templated .wait_in (txwr_fifo_wait)); // Templated
.din (txwr_packet[PW-1:0]), // Templated
.rd_en (txwr_fifo_read)); // Templated
//Read request fifo (from slave) //Read request fifo (from slave)
fifo_async #(.DW(104), .AW(5)) txrd_fifo( fifo_cdc #(.DW(104), .AW(5)) txrd_fifo(
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.full (txrd_wait), // Templated .wait_out (txrd_wait), // Templated
.prog_full (), // Templated .access_out (txrd_fifo_access), // Templated
.dout (txrd_fifo_packet[PW-1:0]), // Templated .packet_out (txrd_fifo_packet[PW-1:0]), // Templated
.empty (txrd_fifo_empty), // Templated // Inputs
.valid (), // Templated .clk_in (sys_clk), // Templated
// Inputs .clk_out (tx_lclk_div4), // Templated
.reset (reset), // Templated .reset (reset), // Templated
.wr_clk (sys_clk), // Templated .access_in (txrd_access), // Templated
.rd_clk (tx_lclk_div4), // Templated .packet_in (txrd_packet[PW-1:0]), // Templated
.wr_en (txrd_access), // Templated .wait_in (txrd_fifo_wait)); // Templated
.din (txrd_packet[PW-1:0]), // Templated
.rd_en (txrd_fifo_read)); // Templated
//Read response fifo (from master) //Read response fifo (from master)
fifo_async #(.DW(104), .AW(5)) txrr_fifo( fifo_cdc #(.DW(104), .AW(5)) txrr_fifo(
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.full (txrr_wait), // Templated .wait_out (txrr_wait), // Templated
.prog_full (), // Templated .access_out (txrr_fifo_access), // Templated
.dout (txrr_fifo_packet[PW-1:0]), // Templated .packet_out (txrr_fifo_packet[PW-1:0]), // Templated
.empty (txrr_fifo_empty), // Templated // Inputs
.valid (), // Templated .clk_in (sys_clk), // Templated
// Inputs .clk_out (tx_lclk_div4), // Templated
.reset (reset), // Templated .reset (reset), // Templated
.wr_clk (sys_clk), // Templated .access_in (txrr_access), // Templated
.rd_clk (tx_lclk_div4), // Templated .packet_in (txrr_packet[PW-1:0]), // Templated
.wr_en (txrr_access), // Templated .wait_in (txrr_fifo_wait)); // Templated
.din (txrr_packet[PW-1:0]), // Templated
.rd_en (txrr_fifo_read)); // Templated
/************************************************************/ /************************************************************/
@ -210,18 +204,18 @@ module etx(/*AUTOARG*/
*/ */
edma etx_dma (/*AUTOINST*/ edma etx_dma (/*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_dma_dout[DW-1:0]), // Templated .mi_dout (mi_dma_dout[DW-1:0]), // Templated
.edma_access (edma_access), // Templated .edma_access (edma_access), // Templated
.edma_packet (edma_packet[PW-1:0]), .edma_packet (edma_packet[PW-1:0]),
// Inputs // Inputs
.reset (reset), .reset (reset),
.clk (tx_lclk_div4), // Templated .clk (tx_lclk_div4), // Templated
.mi_en (mi_dma_en), // Templated .mi_en (mi_dma_en), // Templated
.mi_we (mi_we), .mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]), .mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[63:0]), .mi_din (mi_din[63:0]),
.edma_wait (edma_wait)); .edma_wait (edma_wait));
/************************************************************/ /************************************************************/
/*ELINK TRANSMIT ARBITER */ /*ELINK TRANSMIT ARBITER */
@ -230,29 +224,29 @@ module etx(/*AUTOARG*/
etx_arbiter etx_arbiter (.clk (tx_lclk_div4), etx_arbiter etx_arbiter (.clk (tx_lclk_div4),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.txwr_fifo_read (txwr_fifo_read), .txwr_fifo_wait (txwr_fifo_wait),
.txrd_fifo_read (txrd_fifo_read), .txrd_fifo_wait (txrd_fifo_wait),
.txrr_fifo_read (txrr_fifo_read), .txrr_fifo_wait (txrr_fifo_wait),
.edma_wait (edma_wait), .edma_wait (edma_wait),
.etx_access (etx_access), .etx_access (etx_access),
.etx_packet (etx_packet[PW-1:0]), .etx_packet (etx_packet[PW-1:0]),
.etx_rr (etx_rr), .etx_rr (etx_rr),
// Inputs // Inputs
.reset (reset), .reset (reset),
.txwr_fifo_empty (txwr_fifo_empty), .txwr_fifo_access (txwr_fifo_access),
.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]), .txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
.txrd_fifo_empty (txrd_fifo_empty), .txrd_fifo_access (txrd_fifo_access),
.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]), .txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
.txrr_fifo_empty (txrr_fifo_empty), .txrr_fifo_access (txrr_fifo_access),
.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]), .txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
.edma_access (edma_access), .edma_access (edma_access),
.edma_packet (edma_packet[PW-1:0]), .edma_packet (edma_packet[PW-1:0]),
.ctrlmode_bypass (ctrlmode_bypass),
.ctrlmode (ctrlmode[3:0]),
.etx_rd_wait (etx_rd_wait), .etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait), .etx_wr_wait (etx_wr_wait),
.etx_io_wait (etx_io_wait), .etx_io_wait (etx_io_wait),
.etx_cfg_wait (etx_cfg_wait)); .etx_cfg_wait (etx_cfg_wait),
.ctrlmode_bypass (ctrlmode_bypass),
.ctrlmode (ctrlmode[3:0]));
/************************************************************/ /************************************************************/
@ -264,32 +258,33 @@ module etx(/*AUTOARG*/
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), .mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), .mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), .mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
.clk (tx_lclk_div4), .clk (tx_lclk_div4),
.wait_in (etx_cfg_wait),
); );
*/ */
defparam etx_cfgif.RX =0; defparam etx_cfgif.RX =0;
ecfg_if etx_cfgif (.mi_dout3 (64'b0), ecfg_if etx_cfgif (.mi_dout3 (64'b0),
/*AUTOINST*/ .wait_out (),//TODO:connect
// Outputs /*AUTOINST*/
.wait_out (etx_cfg_wait), // Templated // Outputs
.mi_mmu_en (mi_mmu_en), .mi_mmu_en (mi_mmu_en),
.mi_dma_en (mi_dma_en), .mi_dma_en (mi_dma_en),
.mi_cfg_en (mi_cfg_en), .mi_cfg_en (mi_cfg_en),
.mi_we (mi_we), .mi_we (mi_we),
.mi_addr (mi_addr[14:0]), .mi_addr (mi_addr[14:0]),
.mi_din (mi_din[63:0]), .mi_din (mi_din[63:0]),
.access_out (etx_cfg_access), // Templated .access_out (etx_cfg_access), // Templated
.packet_out (etx_cfg_packet[PW-1:0]), // Templated .packet_out (etx_cfg_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk (tx_lclk_div4), // Templated .clk (tx_lclk_div4), // Templated
.reset (reset), .reset (reset),
.access_in (etx_access), // Templated .access_in (etx_access), // Templated
.packet_in (etx_packet[PW-1:0]), // Templated .packet_in (etx_packet[PW-1:0]), // Templated
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated .mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated .mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated .mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
.wait_in (etx_wait)); // Templated .wait_in (etx_cfg_wait)); // Templated
/************************************************************/ /************************************************************/
/* ETX CONFIGURATION REGISTERS */ /* ETX CONFIGURATION REGISTERS */
@ -300,23 +295,28 @@ module etx(/*AUTOARG*/
); );
*/ */
assign tx_status[15:0] = {2'b0, //15:14 //todo: make more useufl
etx_rd_wait, //13 assign tx_status[15:0] = 16'b0;
etx_wr_wait, //12 /*
txrr_fifo_read, //11
txrr_wait, //10
txrr_access, //9
txrd_fifo_read, //8
txrd_wait, //7
txrd_access, //6
txwr_fifo_read, //5
txwr_wait, //4
txwr_access, //3
txrr_fifo_full, //2
txrd_fifo_full, //1
txwr_fifo_full //0
};
{2'b0, //15:14
etx_rd_wait, //13
etx_wr_wait, //12
txrr_fifo_read, //11
txrr_wait, //10
txrr_access, //9
txrd_fifo_read, //8
txrd_wait, //7
txrd_access, //6
txwr_fifo_read, //5
txwr_wait, //4
txwr_access, //3
1'b0, //2
1'b0, //1
1'b0 //0
};
*/
ecfg_tx etx_cfg ( ecfg_tx etx_cfg (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
@ -374,7 +374,8 @@ module etx(/*AUTOARG*/
.emesh_\(.*\)_out (emmu_\1[]), .emesh_\(.*\)_out (emmu_\1[]),
.mmu_en (mmu_enable), .mmu_en (mmu_enable),
.mmu_bp (etx_rr), .mmu_bp (etx_rr),
.clk (tx_lclk_div4), .rd_clk (tx_lclk_div4),
.wr_clk (tx_lclk_div4),
.emmu_access_out (emmu_access), .emmu_access_out (emmu_access),
.emmu_packet_out (emmu_packet[PW-1:0]), .emmu_packet_out (emmu_packet[PW-1:0]),
.mi_dout (mi_mmu_dout[DW-1:0]), .mi_dout (mi_mmu_dout[DW-1:0]),
@ -386,23 +387,24 @@ module etx(/*AUTOARG*/
emmu etx_mmu ( emmu etx_mmu (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated .mi_dout (mi_mmu_dout[DW-1:0]), // Templated
.emesh_access_out (emmu_access), // Templated .emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated .emesh_packet_out (emmu_packet[PW-1:0]), // Templated
.emesh_packet_hi_out (), // Templated .emesh_packet_hi_out (), // Templated
// Inputs // Inputs
.reset (reset), .reset (reset),
.clk (tx_lclk_div4), // Templated .rd_clk (tx_lclk_div4), // Templated
.mmu_en (mmu_enable), // Templated .wr_clk (tx_lclk_div4), // Templated
.mmu_bp (etx_rr), // Templated .mmu_en (mmu_enable), // Templated
.mi_en (mi_mmu_en), // Templated .mmu_bp (etx_rr), // Templated
.mi_we (mi_we), .mi_en (mi_mmu_en), // Templated
.mi_addr (mi_addr[14:0]), .mi_we (mi_we),
.mi_din (mi_din[DW-1:0]), .mi_addr (mi_addr[14:0]),
.emesh_access_in (etx_remap_access), // Templated .mi_din (mi_din[DW-1:0]),
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated .emesh_access_in (etx_remap_access), // Templated
.emesh_wait_in (etx_wait)); // Templated .emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (etx_wait)); // Templated
/************************************************************/ /************************************************************/