FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Adding count/almost full to fifo

Browse Source
This commit is contained in:
Andreas Olofsson 2015-12-08 21:10:17 -05:00
parent 71b467728d
commit 22976b781d
1 changed files with 74 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

100
common/hdl/oh_fifo_sync.v
View File

@ -1,84 +1,90 @@
/*
########################################################################
Generic small FIFO using distributed memory
Caution: There is no protection against overflow or underflow,
driving logic should avoid wen on full or ren on empty.
########################################################################
*/
module fifo_sync
#(
// Address width (must be 5 => 32-deep FIFO)??
parameter AW = 5,
// Data width
parameter DW = 16
)
(
input clk,
input reset,
input [DW-1:0] wr_data,
input wr_en,
input rd_en,
output wire [DW-1:0] rd_data,
output reg rd_empty,
output reg wr_full
module oh_fifo_sync (/*AUTOARG*/
// Outputs
dout, empty, full, almost_full,
// Inputs
clk, nreset, din, wr_en, rd_en
);
//#####################################################################
//# PARAMETERS
//#####################################################################
parameter DEPTH = 4;
parameter DW = 104;
parameter ALMOST_FULL = DEPTH-1;
localparam AW = $clog2(DEPTH);
//#####################################################################
//# INTERFACE
//#####################################################################
//clk/reset
input clk;
input nreset;
//write port
input [DW-1:0] din;
input wr_en;
//Read port
input rd_en;
output [DW-1:0] dout;
//Status
output empty;
output full;
output almost_full;
//#####################################################################
//# BODY
//#####################################################################
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
reg [AW-1:0] count;
reg [AW:0] count;
always @ ( posedge clk ) begin
if( reset )
assign empty = (count[AW:0]==0);
assign almost_full = (count[AW:0] >=ALMOST_FULL);
assign full = (count==DEPTH);
always @ ( posedge clk or negedge nreset)
if(!nreset)
begin
wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0;
count[AW-1:0] <= 'b0;
rd_empty <= 1'b1;
wr_full <= 1'b0;
end else
begin
if( wr_en & rd_en )
end
else if(wr_en & rd_en)
begin
wr_addr <= wr_addr + 'd1;
rd_addr <= rd_addr + 'd1;
end
else if( wr_en )
else if(wr_en)
begin
wr_addr <= wr_addr + 'd1;
count <= count + 'd1;
rd_empty <= 1'b0;
if( & count )
wr_full <= 1'b1;
end
else if( rd_en )
else if(rd_en)
begin
rd_addr <= rd_addr + 'd1;
count <= count - 'd1;
wr_full <= 1'b0;
if( count == 'd1 )
rd_empty <= 1'b1;
end
end
end
// GENERIC DUAL PORTED MEMORY
defparam mem.DW=DW;
defparam mem.AW=AW;
memory_dp mem (
oh_memory_dp mem (
// Outputs
.rd_data (rd_data[DW-1:0]),
.rd_data (dout[DW-1:0]),
// Inputs
.wr_clk (clk),
.wr_en ({(DW/8){wr_en}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_data (wr_data[DW-1:0]),
.wr_data (din[DW-1:0]),
.rd_clk (clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]));
endmodule // fifo_sync
// Local Variables: