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Merge pull request #111 from nmoroze/master
Some tweaks to padring library
This commit is contained in:
Andreas Olofsson
GitHub
commit
23b26c4a93
@ -30,9 +30,10 @@ module oh_padring
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parameter WE_VSSIO = 8,
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parameter WE_VDD = 8,
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parameter WE_VSS = 8,
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parameter ENABLE_CUTS = 1,
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parameter ENABLE_CUT = 1,
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parameter ENABLE_POC = 1,
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parameter TECH_CFG_WIDTH = 16
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parameter TECH_CFG_WIDTH = 16,
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parameter TECH_RING_WIDTH = 8
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)
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(
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//CONTINUOUS GROUND
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@ -48,7 +49,7 @@ module oh_padring
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input [NO_GPIO*8-1:0] no_cfg, // config
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input [NO_GPIO-1:0] no_ie, // input enable
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input [NO_GPIO-1:0] no_oen, // output enable (bar)
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input [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
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inout [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
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//SOUTH
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inout [SO_DOMAINS-1:0] so_vddio,
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inout [SO_DOMAINS-1:0] so_vssio,
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@ -58,7 +59,7 @@ module oh_padring
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input [SO_GPIO*8-1:0] so_cfg, // config
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input [SO_GPIO-1:0] so_ie, // input enable
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input [SO_GPIO-1:0] so_oen, // output enable (bar)
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input [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
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inout [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
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//EAST
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inout [EA_DOMAINS-1:0] ea_vddio,
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inout [EA_DOMAINS-1:0] ea_vssio,
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@ -68,7 +69,7 @@ module oh_padring
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input [EA_GPIO*8-1:0] ea_cfg, // config
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input [EA_GPIO-1:0] ea_ie, // input enable
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input [EA_GPIO-1:0] ea_oen, // output enable (bar)
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input [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
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inout [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
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//WEST
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inout [WE_DOMAINS-1:0] we_vddio,
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inout [WE_DOMAINS-1:0] we_vssio,
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@ -78,7 +79,7 @@ module oh_padring
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input [WE_GPIO*8-1:0] we_cfg, // config
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input [WE_GPIO-1:0] we_ie, // input enable
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input [WE_GPIO-1:0] we_oen, // output enable (bar)
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input [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
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inout [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
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);
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@ -88,6 +89,8 @@ module oh_padring
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wire [WE_DOMAINS-1:0] we_poc;
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wire [EA_DOMAINS-1:0] ea_poc;
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wire [TECH_RING_WIDTH-1:0] ring;
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generate
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genvar i;
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@ -117,6 +120,7 @@ module oh_padring
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.vddio (no_vddio[i]),
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.vssio (no_vssio[i]),
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.poc (no_poc[i]),
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.ring(ring),
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// Inputs
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.dout (no_dout[NO_GPIO-1:0]),
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.oen (no_oen[NO_GPIO-1:0]),
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@ -151,6 +155,7 @@ module oh_padring
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.vddio (so_vddio[i]),
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.vssio (so_vssio[i]),
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.poc (so_poc[i]),
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.ring(ring),
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// Inputs
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.dout (so_dout[SO_GPIO-1:0]),
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.oen (so_oen[SO_GPIO-1:0]),
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@ -186,6 +191,7 @@ module oh_padring
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.vddio (ea_vddio[i]),
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.vssio (ea_vssio[i]),
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.poc (ea_poc[i]),
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.ring(ring),
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// Inputs
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.dout (ea_dout[EA_GPIO-1:0]),
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.oen (ea_oen[EA_GPIO-1:0]),
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@ -222,6 +228,7 @@ module oh_padring
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.vddio (we_vddio[i]),
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.vssio (we_vssio[i]),
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.poc (we_poc[i]),
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.ring(ring),
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// Inputs
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.dout (we_dout[WE_GPIO-1:0]),
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.oen (we_oen[WE_GPIO-1:0]),
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@ -1,10 +1,10 @@
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//#############################################################################
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//# Function: A Padring IO Domain #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module oh_pads_domain
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module oh_pads_domain
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#(parameter TYPE = "SOFT",// asic cell type selector
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parameter DIR = "NO", // "NO", "SO", "EA", "WE"
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parameter NGPIO = 8, // total IO signal pads
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@ -15,7 +15,8 @@ module oh_pads_domain
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parameter POC = 1, // 1 = place poc cell
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parameter LEFTCUT = 1, // 1 = place cut on left (seen from center)
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parameter RIGHTCUT = 1, // 1 = place cut on right (seen from center
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parameter TECH_CFG_WIDTH = 16
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parameter TECH_CFG_WIDTH = 16,
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parameter TECH_RING_WIDTH = 8
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)
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(//pad
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inout [NGPIO-1:0] pad, // pad
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@ -25,17 +26,20 @@ module oh_pads_domain
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inout vdd, // core supply
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inout vss, // common ground
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inout poc, // power-on-ctrl
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inout [TECH_RING_WIDTH-1:0] ring,
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//core facing signals
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input [NGPIO-1:0] dout, // data to drive to pad
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output [NGPIO-1:0] din, // data from pad
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input [NGPIO-1:0] oen, // output enable (bar)
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input [NGPIO-1:0] ie, // input enable
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input [NGPIO*8-1:0] cfg, // io config
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input [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
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inout [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
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);
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generate
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genvar i;
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genvar i;
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//#####################
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//# IO BUFFERS
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@ -44,7 +48,8 @@ module oh_pads_domain
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for(i=0;i<NGPIO;i=i+1)
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begin : padio
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asic_iobuf #(.DIR(DIR),
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.TYPE(TYPE))
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.TYPE(TYPE),
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.TECH_CFG_WIDTH(TECH_CFG_WIDTH))
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i0 (// data to core
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.din (din[i]),
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// data from core
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@ -61,7 +66,9 @@ module oh_pads_domain
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.vddio (vddio),
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.vssio (vssio),
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.pad (pad[i]),
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.ring(ring),
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.tech_cfg(tech_cfg[i*TECH_CFG_WIDTH+:TECH_CFG_WIDTH]));
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end
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@ -69,7 +76,7 @@ module oh_pads_domain
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//# IO SUPPLY PINS
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//######################
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for(i=0;i<NVDDIO;i=i+1)
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for(i=0;i<NVDDIO;i=i+1)
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begin : padvddio
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asic_iovddio #(.DIR(DIR),
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.TYPE(TYPE))
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@ -77,14 +84,15 @@ module oh_pads_domain
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.ring(ring),
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.poc (poc));
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end
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end
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//######################
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//# IO GROUND PINS
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//######################
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//######################
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for(i=0;i<NVSSIO;i=i+1)
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for(i=0;i<NVSSIO;i=i+1)
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begin: padvssio
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asic_iovssio #(.DIR(DIR),
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.TYPE(TYPE))
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@ -92,13 +100,14 @@ module oh_pads_domain
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.ring(ring),
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.poc (poc));
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end
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//######################
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//# CORE SUPPLY PINS
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//######################
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for(i=0;i<NVDD;i=i+1)
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for(i=0;i<NVDD;i=i+1)
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begin: padvdd
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asic_iovdd #(.DIR(DIR),
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.TYPE(TYPE))
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@ -106,13 +115,14 @@ module oh_pads_domain
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.ring(ring),
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.poc (poc));
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end
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end
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//######################
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//# CORE GROUND PINS
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//######################
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for(i=0;i<NVSS;i=i+1)
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//######################
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for(i=0;i<NVSS;i=i+1)
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begin: padvss
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asic_iovss #(.DIR(DIR),
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.TYPE(TYPE))
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@ -120,12 +130,13 @@ module oh_pads_domain
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.ring(ring),
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.poc (poc));
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end
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//######################
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//# CUT CELLS
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//######################
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//######################
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if (LEFTCUT==1)
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begin: padcutleft
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asic_iocut #(.DIR(DIR),
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@ -136,7 +147,7 @@ module oh_pads_domain
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.vssio (vssio),
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.poc (poc));
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end
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if (RIGHTCUT==1)
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begin: padcutright
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asic_iocut #(.DIR(DIR),
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@ -147,7 +158,7 @@ module oh_pads_domain
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.vssio (vssio),
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.poc (poc));
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end
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//######################
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//# POWER ON CONTROL
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//######################
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@ -163,10 +174,10 @@ module oh_pads_domain
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end
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endgenerate
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endmodule
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// Local Variables:
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// verilog-library-directories:("." )
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// verilog-library-directories:("." )
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// End:
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