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Merge pull request #111 from nmoroze/master

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Some tweaks to padring library
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Andreas Olofsson 2021-11-26 21:15:20 -05:00 committed by GitHub
commit 23b26c4a93
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2 changed files with 45 additions and 27 deletions
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19
padring/hdl/oh_padring.v
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@ -30,9 +30,10 @@ module oh_padring
parameter WE_VSSIO = 8, parameter WE_VSSIO = 8,
parameter WE_VDD = 8, parameter WE_VDD = 8,
parameter WE_VSS = 8, parameter WE_VSS = 8,
parameter ENABLE_CUTS = 1, parameter ENABLE_CUT = 1,
parameter ENABLE_POC = 1, parameter ENABLE_POC = 1,
parameter TECH_CFG_WIDTH = 16 parameter TECH_CFG_WIDTH = 16,
parameter TECH_RING_WIDTH = 8
) )
( (
//CONTINUOUS GROUND //CONTINUOUS GROUND
@ -48,7 +49,7 @@ module oh_padring
input [NO_GPIO*8-1:0] no_cfg, // config input [NO_GPIO*8-1:0] no_cfg, // config
input [NO_GPIO-1:0] no_ie, // input enable input [NO_GPIO-1:0] no_ie, // input enable
input [NO_GPIO-1:0] no_oen, // output enable (bar) input [NO_GPIO-1:0] no_oen, // output enable (bar)
input [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg, inout [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
//SOUTH //SOUTH
inout [SO_DOMAINS-1:0] so_vddio, inout [SO_DOMAINS-1:0] so_vddio,
inout [SO_DOMAINS-1:0] so_vssio, inout [SO_DOMAINS-1:0] so_vssio,
@ -58,7 +59,7 @@ module oh_padring
input [SO_GPIO*8-1:0] so_cfg, // config input [SO_GPIO*8-1:0] so_cfg, // config
input [SO_GPIO-1:0] so_ie, // input enable input [SO_GPIO-1:0] so_ie, // input enable
input [SO_GPIO-1:0] so_oen, // output enable (bar) input [SO_GPIO-1:0] so_oen, // output enable (bar)
input [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg, inout [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
//EAST //EAST
inout [EA_DOMAINS-1:0] ea_vddio, inout [EA_DOMAINS-1:0] ea_vddio,
inout [EA_DOMAINS-1:0] ea_vssio, inout [EA_DOMAINS-1:0] ea_vssio,
@ -68,7 +69,7 @@ module oh_padring
input [EA_GPIO*8-1:0] ea_cfg, // config input [EA_GPIO*8-1:0] ea_cfg, // config
input [EA_GPIO-1:0] ea_ie, // input enable input [EA_GPIO-1:0] ea_ie, // input enable
input [EA_GPIO-1:0] ea_oen, // output enable (bar) input [EA_GPIO-1:0] ea_oen, // output enable (bar)
input [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg, inout [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
//WEST //WEST
inout [WE_DOMAINS-1:0] we_vddio, inout [WE_DOMAINS-1:0] we_vddio,
inout [WE_DOMAINS-1:0] we_vssio, inout [WE_DOMAINS-1:0] we_vssio,
@ -78,7 +79,7 @@ module oh_padring
input [WE_GPIO*8-1:0] we_cfg, // config input [WE_GPIO*8-1:0] we_cfg, // config
input [WE_GPIO-1:0] we_ie, // input enable input [WE_GPIO-1:0] we_ie, // input enable
input [WE_GPIO-1:0] we_oen, // output enable (bar) input [WE_GPIO-1:0] we_oen, // output enable (bar)
input [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg inout [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
); );
@ -88,6 +89,8 @@ module oh_padring
wire [WE_DOMAINS-1:0] we_poc; wire [WE_DOMAINS-1:0] we_poc;
wire [EA_DOMAINS-1:0] ea_poc; wire [EA_DOMAINS-1:0] ea_poc;
wire [TECH_RING_WIDTH-1:0] ring;
generate generate
genvar i; genvar i;
@ -117,6 +120,7 @@ module oh_padring
.vddio (no_vddio[i]), .vddio (no_vddio[i]),
.vssio (no_vssio[i]), .vssio (no_vssio[i]),
.poc (no_poc[i]), .poc (no_poc[i]),
.ring(ring),
// Inputs // Inputs
.dout (no_dout[NO_GPIO-1:0]), .dout (no_dout[NO_GPIO-1:0]),
.oen (no_oen[NO_GPIO-1:0]), .oen (no_oen[NO_GPIO-1:0]),
@ -151,6 +155,7 @@ module oh_padring
.vddio (so_vddio[i]), .vddio (so_vddio[i]),
.vssio (so_vssio[i]), .vssio (so_vssio[i]),
.poc (so_poc[i]), .poc (so_poc[i]),
.ring(ring),
// Inputs // Inputs
.dout (so_dout[SO_GPIO-1:0]), .dout (so_dout[SO_GPIO-1:0]),
.oen (so_oen[SO_GPIO-1:0]), .oen (so_oen[SO_GPIO-1:0]),
@ -186,6 +191,7 @@ module oh_padring
.vddio (ea_vddio[i]), .vddio (ea_vddio[i]),
.vssio (ea_vssio[i]), .vssio (ea_vssio[i]),
.poc (ea_poc[i]), .poc (ea_poc[i]),
.ring(ring),
// Inputs // Inputs
.dout (ea_dout[EA_GPIO-1:0]), .dout (ea_dout[EA_GPIO-1:0]),
.oen (ea_oen[EA_GPIO-1:0]), .oen (ea_oen[EA_GPIO-1:0]),
@ -222,6 +228,7 @@ module oh_padring
.vddio (we_vddio[i]), .vddio (we_vddio[i]),
.vssio (we_vssio[i]), .vssio (we_vssio[i]),
.poc (we_poc[i]), .poc (we_poc[i]),
.ring(ring),
// Inputs // Inputs
.dout (we_dout[WE_GPIO-1:0]), .dout (we_dout[WE_GPIO-1:0]),
.oen (we_oen[WE_GPIO-1:0]), .oen (we_oen[WE_GPIO-1:0]),

53
padring/hdl/oh_pads_domain.v
View File

@ -1,10 +1,10 @@
//############################################################################# //#############################################################################
//# Function: A Padring IO Domain # //# Function: A Padring IO Domain #
//# Copyright: OH Project Authors. ALl rights Reserved. # //# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) # //# License: MIT (see LICENSE file in OH repository) #
//############################################################################# //#############################################################################
module oh_pads_domain module oh_pads_domain
#(parameter TYPE = "SOFT",// asic cell type selector #(parameter TYPE = "SOFT",// asic cell type selector
parameter DIR = "NO", // "NO", "SO", "EA", "WE" parameter DIR = "NO", // "NO", "SO", "EA", "WE"
parameter NGPIO = 8, // total IO signal pads parameter NGPIO = 8, // total IO signal pads
@ -15,7 +15,8 @@ module oh_pads_domain
parameter POC = 1, // 1 = place poc cell parameter POC = 1, // 1 = place poc cell
parameter LEFTCUT = 1, // 1 = place cut on left (seen from center) parameter LEFTCUT = 1, // 1 = place cut on left (seen from center)
parameter RIGHTCUT = 1, // 1 = place cut on right (seen from center parameter RIGHTCUT = 1, // 1 = place cut on right (seen from center
parameter TECH_CFG_WIDTH = 16 parameter TECH_CFG_WIDTH = 16,
parameter TECH_RING_WIDTH = 8
) )
(//pad (//pad
inout [NGPIO-1:0] pad, // pad inout [NGPIO-1:0] pad, // pad
@ -25,17 +26,20 @@ module oh_pads_domain
inout vdd, // core supply inout vdd, // core supply
inout vss, // common ground inout vss, // common ground
inout poc, // power-on-ctrl inout poc, // power-on-ctrl
inout [TECH_RING_WIDTH-1:0] ring,
//core facing signals //core facing signals
input [NGPIO-1:0] dout, // data to drive to pad input [NGPIO-1:0] dout, // data to drive to pad
output [NGPIO-1:0] din, // data from pad output [NGPIO-1:0] din, // data from pad
input [NGPIO-1:0] oen, // output enable (bar) input [NGPIO-1:0] oen, // output enable (bar)
input [NGPIO-1:0] ie, // input enable input [NGPIO-1:0] ie, // input enable
input [NGPIO*8-1:0] cfg, // io config input [NGPIO*8-1:0] cfg, // io config
input [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config inout [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
); );
generate generate
genvar i; genvar i;
//##################### //#####################
//# IO BUFFERS //# IO BUFFERS
@ -44,7 +48,8 @@ module oh_pads_domain
for(i=0;i<NGPIO;i=i+1) for(i=0;i<NGPIO;i=i+1)
begin : padio begin : padio
asic_iobuf #(.DIR(DIR), asic_iobuf #(.DIR(DIR),
.TYPE(TYPE)) .TYPE(TYPE),
.TECH_CFG_WIDTH(TECH_CFG_WIDTH))
i0 (// data to core i0 (// data to core
.din (din[i]), .din (din[i]),
// data from core // data from core
@ -61,7 +66,9 @@ module oh_pads_domain
.vddio (vddio), .vddio (vddio),
.vssio (vssio), .vssio (vssio),
.pad (pad[i]), .pad (pad[i]),
.ring(ring),
.tech_cfg(tech_cfg[i*TECH_CFG_WIDTH+:TECH_CFG_WIDTH])); .tech_cfg(tech_cfg[i*TECH_CFG_WIDTH+:TECH_CFG_WIDTH]));
end end
@ -69,7 +76,7 @@ module oh_pads_domain
//# IO SUPPLY PINS //# IO SUPPLY PINS
//###################### //######################
for(i=0;i<NVDDIO;i=i+1) for(i=0;i<NVDDIO;i=i+1)
begin : padvddio begin : padvddio
asic_iovddio #(.DIR(DIR), asic_iovddio #(.DIR(DIR),
.TYPE(TYPE)) .TYPE(TYPE))
@ -77,14 +84,15 @@ module oh_pads_domain
.vss (vss), .vss (vss),
.vddio (vddio), .vddio (vddio),
.vssio (vssio), .vssio (vssio),
.ring(ring),
.poc (poc)); .poc (poc));
end end
//###################### //######################
//# IO GROUND PINS //# IO GROUND PINS
//###################### //######################
for(i=0;i<NVSSIO;i=i+1) for(i=0;i<NVSSIO;i=i+1)
begin: padvssio begin: padvssio
asic_iovssio #(.DIR(DIR), asic_iovssio #(.DIR(DIR),
.TYPE(TYPE)) .TYPE(TYPE))
@ -92,13 +100,14 @@ module oh_pads_domain
.vss (vss), .vss (vss),
.vddio (vddio), .vddio (vddio),
.vssio (vssio), .vssio (vssio),
.ring(ring),
.poc (poc)); .poc (poc));
end end
//###################### //######################
//# CORE SUPPLY PINS //# CORE SUPPLY PINS
//###################### //######################
for(i=0;i<NVDD;i=i+1) for(i=0;i<NVDD;i=i+1)
begin: padvdd begin: padvdd
asic_iovdd #(.DIR(DIR), asic_iovdd #(.DIR(DIR),
.TYPE(TYPE)) .TYPE(TYPE))
@ -106,13 +115,14 @@ module oh_pads_domain
.vss (vss), .vss (vss),
.vddio (vddio), .vddio (vddio),
.vssio (vssio), .vssio (vssio),
.ring(ring),
.poc (poc)); .poc (poc));
end end
//###################### //######################
//# CORE GROUND PINS //# CORE GROUND PINS
//###################### //######################
for(i=0;i<NVSS;i=i+1) for(i=0;i<NVSS;i=i+1)
begin: padvss begin: padvss
asic_iovss #(.DIR(DIR), asic_iovss #(.DIR(DIR),
.TYPE(TYPE)) .TYPE(TYPE))
@ -120,12 +130,13 @@ module oh_pads_domain
.vss (vss), .vss (vss),
.vddio (vddio), .vddio (vddio),
.vssio (vssio), .vssio (vssio),
.ring(ring),
.poc (poc)); .poc (poc));
end end
//###################### //######################
//# CUT CELLS //# CUT CELLS
//###################### //######################
if (LEFTCUT==1) if (LEFTCUT==1)
begin: padcutleft begin: padcutleft
asic_iocut #(.DIR(DIR), asic_iocut #(.DIR(DIR),
@ -136,7 +147,7 @@ module oh_pads_domain
.vssio (vssio), .vssio (vssio),
.poc (poc)); .poc (poc));
end end
if (RIGHTCUT==1) if (RIGHTCUT==1)
begin: padcutright begin: padcutright
asic_iocut #(.DIR(DIR), asic_iocut #(.DIR(DIR),
@ -147,7 +158,7 @@ module oh_pads_domain
.vssio (vssio), .vssio (vssio),
.poc (poc)); .poc (poc));
end end
//###################### //######################
//# POWER ON CONTROL //# POWER ON CONTROL
//###################### //######################
@ -163,10 +174,10 @@ module oh_pads_domain
end end
endgenerate endgenerate
endmodule endmodule
// Local Variables: // Local Variables:
// verilog-library-directories:("." ) // verilog-library-directories:("." )
// End: // End: