FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity

fpga/system_build.tcl: Tweak implementation optimization settings

Browse Source 
This is what ADI HDL uses. I trust that they know what they're doing.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
This commit is contained in:
Ola Jeppsson 2017-02-07 18:42:20 +01:00
parent f7e8ddfe7d
commit 23c2f8b383
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/common/fpga/system_build.tcl
View File

@ -39,6 +39,9 @@ report_timing_summary -file timing_synth.log
###########################################################
# PLACE AND ROUTE
###########################################################
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
set_property STRATEGY "Performance_Explore" [get_runs impl_1]
launch_runs impl_1
wait_on_run impl_1
open_run impl_1