cleanup

elink/dv/test.memh

@@ -1,9 +1,44 @@
 00000000_00000000_00000000_00 //dummy
-00000000_11111111_80800000_0b //write to epiphany
-00000000_22222222_80800008_0b //write to epiphany
-00000000_33333333_80800010_0b //write to epiphany
-00000000_44444444_80800018_0b //write to epiphany
-00000000_55555555_80800020_0b //write to epiphany
+00000000_01111111_80800000_0b //write to epiphany
+00000000_02222222_80800008_0b //write to epiphany
+00000000_03333333_80800010_0b //write to epiphany
+00000000_04444444_80800018_0b //write to epiphany
+00000000_05555555_80800020_0b //write to epiphany
+00000000_11111111_80800100_0b //write to epiphany
+00000000_12222222_80800108_0b //write to epiphany
+00000000_13333333_80800110_0b //write to epiphany
+00000000_14444444_80800118_0b //write to epiphany
+00000000_15555555_80800120_0b //write to epiphany
+00000000_21111111_80800200_0b //write to epiphany
+00000000_22222222_80800208_0b //write to epiphany
+00000000_23333333_80800210_0b //write to epiphany
+00000000_24444444_80800218_0b //write to epiphany
+00000000_25555555_80800220_0b //write to epiphany
+00000000_31111111_80800300_0b //write to epiphany
+00000000_32222222_80800308_0b //write to epiphany
+00000000_33333333_80800310_0b //write to epiphany
+00000000_34444444_80800318_0b //write to epiphany
+00000000_35555555_80800320_0b //write to epiphany
+00000000_41111111_80800400_0b //write to epiphany
+00000000_42222222_80800408_0b //write to epiphany
+00000000_43333333_80800410_0b //write to epiphany
+00000000_44444444_80800418_0b //write to epiphany
+00000000_45555555_80800420_0b //write to epiphany
+00000000_51111111_80800500_0b //write to epiphany
+00000000_52222222_80800508_0b //write to epiphany
+00000000_53333333_80800510_0b //write to epiphany
+00000000_54444444_80800518_0b //write to epiphany
+00000000_55555555_80800520_0b //write to epiphany
+00000000_61111111_80800600_0b //write to epiphany
+00000000_62222222_80800608_0b //write to epiphany
+00000000_63333333_80800610_0b //write to epiphany
+00000000_64444444_80800618_0b //write to epiphany
+00000000_65555555_80800620_0b //write to epiphany
+00000000_71111111_80800700_0b //write to epiphany
+00000000_72222222_80800708_0b //write to epiphany
+00000000_73333333_80800710_0b //write to epiphany
+00000000_74444444_80800718_0b //write to epiphany
+00000000_75555555_80800720_0b //write to epiphany
 810D0000_DEADBEEF_80800000_09 //read
 810D0008_DEADBEEF_80800008_09 //read
 810D0008_DEADBEEF_80800010_09 //read

elink/hdl/eclocks.v

@@ -7,10 +7,15 @@
  #
  #  tx_lclk90    - DDR "Clock" for IO (500MHz)
  #
- #  rx_lclk      - High speed RX clock for IO (clkin freq)
+ #  rx_lclk      - High speed RX clock for IO (300MHz phase shifted)
  #
  #  rx_lclk_div4 - Low speed RX clock for logic (75MHz)
  ############################################################################
+ 
+ 
+ 
+ 
+ 
  */
 
 `include "elink_constants.v"

elink/hdl/erx_io.v

@@ -1,4 +1,4 @@
-/*
+\/*
  This block receives the IO transaction and converts to a 104 bit packet. 
  */
 `include "elink_constants.v"
@@ -266,8 +266,8 @@ module erx_io (/*AUTOARG*/
    //#RX CLOCK
    //###################################
 
-   BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_lclk_pll));
-   BUFIO rx_lclk_bufio_i(.I(rxi_lclk), .O(rx_lclk_iddr));
+   BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_lclk_pll));  //for rest of io
+   BUFIO rx_lclk_bufio_i(.I(rxi_lclk), .O(rx_lclk_iddr));//for iddr
 
    //###################################
    //#IDELAY CIRCUIT

elink/scripts/xilinx/elink_clocks.xdc

@@ -1,14 +0,0 @@
-#AXI Master Clock
-create_clock -period 10 -name m_axi_aclk -waveform {0.000 5} [get_ports m_axi_aclk]
-
-#AXI Slave Clock
-create_clock -period 10 -name s_axi_aclk -waveform {0.000 5} [get_ports s_axi_aclk]
-
-#AXI Slave Config Clock
-create_clock -period 10 -name s_axicfg_aclk -waveform {0.000 5} [get_ports s_axicfg_aclk]
-
-#RX Clock
-create_clock -period 2 -name rx_lclk_p -waveform {0.000 1} [get_ports rx_lclk_p]
-
-#CLKIN
-create_clock -period 10 -name clkin -waveform {0.000 1} [get_ports clkin]

elink/scripts/xilinx/elink_pins.xdc

@@ -1,86 +0,0 @@
-#BANK SELECT
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-
-#SETTING SIGNAL STANDARDS
-set_property IOSTANDARD LVDS_25  [get_ports {rxi*}]
-set_property IOSTANDARD LVDS_25  [get_ports {rxo*}]
-set_property IOSTANDARD LVDS_25  [get_ports {txi_wr_wait_*}]
-set_property IOSTANDARD LVCMOS25 [get_ports {txi_rd_wait_*}]
-set_property IOSTANDARD LVDS_25  [get_ports {txo*}]
-set_property IOSTANDARD LVDS_25  [get_ports {cclk*}]
-
-set_property IOSTANDARD LVCMOS25 [get_ports {start}]
-set_property IOSTANDARD LVCMOS25 [get_ports {chipid}]
-set_property IOSTANDARD LVCMOS25 [get_ports {chip_resetb}]
-set_property IOSTANDARD LVCMOS25 [get_ports {reset}]
-set_property IOSTANDARD LVDS_25  [get_ports {sys_clk*}]
-set_property IOSTANDARD LVDS_25  [get_ports {clkin_*}]
-
-#####################
-# Epiphany Interface
-#####################
-set_property PACKAGE_PIN H16 [get_ports {cclk_p}]
-set_property PACKAGE_PIN H17 [get_ports {cclk_n}]
-set_property PACKAGE_PIN G14 [get_ports {chip_resetb}]
-
-set_property PACKAGE_PIN F16 [get_ports {txo_lclk_p}]
-set_property PACKAGE_PIN F17 [get_ports {txo_lclk_n}]
-set_property PACKAGE_PIN B19 [get_ports {txo_data_p[0]}]
-set_property PACKAGE_PIN A20 [get_ports {txo_data_n[0]}]
-set_property PACKAGE_PIN C20 [get_ports {txo_data_p[1]}]
-set_property PACKAGE_PIN B20 [get_ports {txo_data_n[1]}]
-set_property PACKAGE_PIN D19 [get_ports {txo_data_p[2]}]
-set_property PACKAGE_PIN D20 [get_ports {txo_data_n[2]}]
-set_property PACKAGE_PIN E18 [get_ports {txo_data_p[3]}]
-set_property PACKAGE_PIN E19 [get_ports {txo_data_n[3]}]
-set_property PACKAGE_PIN E17 [get_ports {txo_data_p[4]}]
-set_property PACKAGE_PIN D18 [get_ports {txo_data_n[4]}]
-set_property PACKAGE_PIN F19 [get_ports {txo_data_p[5]}]
-set_property PACKAGE_PIN F20 [get_ports {txo_data_n[5]}]
-set_property PACKAGE_PIN G17 [get_ports {txo_data_p[6]}]
-set_property PACKAGE_PIN G18 [get_ports {txo_data_n[6]}]
-set_property PACKAGE_PIN G19 [get_ports {txo_data_p[7]}]
-set_property PACKAGE_PIN G20 [get_ports {txo_data_n[7]}]
-set_property PACKAGE_PIN H15 [get_ports {txo_frame_p}]
-set_property PACKAGE_PIN G15 [get_ports {txo_frame_n}]
-set_property PACKAGE_PIN J15 [get_ports {txi_rd_wait_p}]
-set_property PACKAGE_PIN J18 [get_ports {txi_wr_wait_p}]
-set_property PACKAGE_PIN H18 [get_ports {txi_wr_wait_n}]
-
-set_property PACKAGE_PIN K17 [get_ports {rxi_lclk_p}]
-set_property PACKAGE_PIN K18 [get_ports {rxi_lclk_n}]
-set_property PACKAGE_PIN K19 [get_ports {rxi_data_p[0]}]
-set_property PACKAGE_PIN J19 [get_ports {rxi_data_n[0]}]
-set_property PACKAGE_PIN L14 [get_ports {rxi_data_p[1]}]
-set_property PACKAGE_PIN L15 [get_ports {rxi_data_n[1]}]
-set_property PACKAGE_PIN L16 [get_ports {rxi_data_p[2]}]
-set_property PACKAGE_PIN L17 [get_ports {rxi_data_n[2]}]
-set_property PACKAGE_PIN M14 [get_ports {rxi_data_p[3]}]
-set_property PACKAGE_PIN M15 [get_ports {rxi_data_n[3]}]
-set_property PACKAGE_PIN L19 [get_ports {rxi_data_p[4]}]
-set_property PACKAGE_PIN L20 [get_ports {rxi_data_n[4]}]
-set_property PACKAGE_PIN M19 [get_ports {rxi_data_p[5]}]
-set_property PACKAGE_PIN M20 [get_ports {rxi_data_n[5]}]
-set_property PACKAGE_PIN M17 [get_ports {rxi_data_p[6]}]
-set_property PACKAGE_PIN M18 [get_ports {rxi_data_n[6]}]
-set_property PACKAGE_PIN N15 [get_ports {rxi_data_p[7]}]
-set_property PACKAGE_PIN N16 [get_ports {rxi_data_n[7]}]
-set_property PACKAGE_PIN J20 [get_ports {rxi_frame_p}]
-set_property PACKAGE_PIN H20 [get_ports {rxi_frame_n}]
-set_property PACKAGE_PIN K14 [get_ports {rxo_rd_wait_p}]
-set_property PACKAGE_PIN J14 [get_ports {rxo_rd_wait_n}]
-set_property PACKAGE_PIN K16 [get_ports {rxo_wr_wait_p}]
-set_property PACKAGE_PIN J16 [get_ports {rxo_wr_wait_n}]
-
-#####################
-# Dummy (only for example)
-#####################
-#MRCC
-set_property PACKAGE_PIN U18 [get_ports {clkin_p}]
-set_property PACKAGE_PIN U19 [get_ports {clkin_n}]
-set_property PACKAGE_PIN U14 [get_ports {sys_clk_p}]
-set_property PACKAGE_PIN U15 [get_ports {sys_clk_p}]
-
-set_property PACKAGE_PIN U12 [get_ports {start}]
-set_property PACKAGE_PIN U13 [get_ports {reset}]

elink/scripts/xilinx/elink_timing.xdc

@@ -1,28 +0,0 @@
-#PLL CLOCK
-create_clock -name pll_clkin -period 10  [get_ports clkin_p]
-
-#SYS_CLK
-create_clock -name sys_clk -period 10 [get_ports sys_clk_p]
-
-#RECEIVER
-create_clock -period 3.333 -name rx_lclk -waveform {0.000 1.666} [get_ports rxi_lclk_p]
-set_input_delay -clock [get_clocks rx_lclk] -max -add_delay 2.5 [get_ports {rxi_data_p[*] rxi_frame_p}]
-set_input_delay -clock [get_clocks rx_lclk] -min -add_delay 0.833 [get_ports {rxi_data_p[*] rxi_frame_p}]
-#set_false_path -rise_from [get_clocks rx_lclk] -through [get_ports {rxi_data_p[*] rxi_frame_p}] -fall_to [get_clocks rx_lclk]
-
-set_input_delay -clock [get_clocks rx_lclk] -clock_fall -max -add_delay 2.5 [get_ports {rxi_data_p[*] rxi_frame_p}]
-set_input_delay -clock [get_clocks rx_lclk] -clock_fall -min -add_delay 0.833 [get_ports {RX_data_p[*] rxi_frame_p}]
-#set_false_path -fall_from [get_clocks rx_lclk] -through [get_ports {rxi_data_p[*] rxi_frame_p}] -rise_to [get_clocks rx_lclk]
-
-
-#TRANSMITTER
-#????
-#create_clock -name tx_lclk -period 2 elink/eclocks/pll_lclk/CLKOUT0
-#create_clock -name tx_lclk90 -period 2 elink/eclocks/pll_lclk/CLKOUT1
-##create_clock -name tx_lclk_div4 -period 8 elink/eclocks/pll_lclk/CLKOUT2
-#set_output_delay -clock tx_lclk 0.5 [get_ports txo_data_*]
-#set_output_delay -clock tx_lclk 0.5 [get_ports txo_frame_*]
-
-
-
-

elink/scripts/xilinx/package_axi_elink.tcl

@@ -1,29 +0,0 @@
-set pwd [file dirname [info script]]
-source $pwd/../../../include/oh.tcl
-
-# ???
-set_msg_config -id {ip_flow 19-459} -suppress
-
-oh::ip::create axi_elink $top_builddir/axi_elink
-
-set elink_src_files [list \
-    "$top_srcdir/common/hdl" \
-    "$top_srcdir/emesh/hdl" \
-    "$top_srcdir/emmu/hdl/emmu.v" \
-    "$top_srcdir/edma/hdl/edma.v" \
-    "$top_srcdir/emailbox/hdl/emailbox.v" \
-    "$top_srcdir/elink/hdl" ]
-set elink_constr_files [list \
-    "$top_srcdir/elink/scripts/xilinx/elink_clocks.xdc" \
-    "$top_srcdir/elink/scripts/xilinx/elink_pins.xdc" \
-    "$top_srcdir/elink/scripts/xilinx/elink_timing.xdc" ]
-set elink_ip_files [concat $elink_src_files $elink_constr_files]
-
-oh::ip::add_files axi_elink $elink_ip_files
-# Does not work / is it needed ?
-#oh::ip::add_constraints $elink_constr_files
-
-oh::ip::set_properties $top_builddir/axi_elink
-
-ipx::save_core [ipx::current_core]
-

elink/scripts/xilinx/read_constraints.tcl

@@ -1,10 +0,0 @@
-set pwd [file dirname [info script]]
-source $pwd/../../../include/oh.tcl
-
-read_xdc $pwd/elink_pins.xdc
-read_xdc $pwd/elink_timing.xdc
-
-# Do we need this?
-#read_xdc $pwd/elink_clocks.xdc
-
-

elink/scripts/xilinx/read_ip.tcl

@@ -1,6 +0,0 @@
-set pwd [file dirname [info script]]
-source $pwd/../../../include/oh.tcl
-
-read_ip $top_srcdir/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci
-read_ip $top_srcdir/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci
-

elink/scripts/xilinx/read_verilog.tcl

@@ -1,58 +0,0 @@
-set pwd [file dirname [info script]]
-source $pwd/../../../include/oh.tcl
-
-#ONLY FOR REFERENCE EXAMPLE
-read_verilog $top_srcdir/elink/hdl/axi_elink.v
-
-#ELINK
-read_verilog $top_srcdir/elink/hdl/elink_constants.v
-read_verilog $top_srcdir/elink/hdl/elink_regmap.v
-read_verilog $top_srcdir/elink/hdl/elink.v
-read_verilog $top_srcdir/elink/hdl/eclocks.v
-read_verilog $top_srcdir/elink/hdl/ereset.v
-read_verilog $top_srcdir/elink/hdl/ecfg_elink.v
-read_verilog $top_srcdir/elink/hdl/ecfg_if.v
-read_verilog $top_srcdir/elink/hdl/erx.v
-read_verilog $top_srcdir/elink/hdl/erx_core.v
-read_verilog $top_srcdir/elink/hdl/erx_fifo.v
-read_verilog $top_srcdir/elink/hdl/erx_cfg.v
-read_verilog $top_srcdir/elink/hdl/erx_arbiter.v
-read_verilog $top_srcdir/elink/hdl/erx_protocol.v
-read_verilog $top_srcdir/elink/hdl/erx_remap.v
-read_verilog $top_srcdir/elink/hdl/erx_io.v
-read_verilog $top_srcdir/elink/hdl/etx.v
-read_verilog $top_srcdir/elink/hdl/etx_core.v
-read_verilog $top_srcdir/elink/hdl/etx_fifo.v
-read_verilog $top_srcdir/elink/hdl/etx_cfg.v
-read_verilog $top_srcdir/elink/hdl/etx_arbiter.v
-read_verilog $top_srcdir/elink/hdl/etx_protocol.v
-read_verilog $top_srcdir/elink/hdl/etx_remap.v
-read_verilog $top_srcdir/elink/hdl/etx_io.v
-read_verilog $top_srcdir/elink/hdl/esaxi.v
-read_verilog $top_srcdir/elink/hdl/emaxi.v
-
-#COMMON
-read_verilog $top_srcdir/common/hdl/toggle2pulse.v
-read_verilog $top_srcdir/common/hdl/synchronizer.v
-read_verilog $top_srcdir/common/hdl/pulse_stretcher.v
-read_verilog $top_srcdir/common/hdl/clock_divider.v
-read_verilog $top_srcdir/common/hdl/arbiter_priority.v
-
-#EMESH
-read_verilog $top_srcdir/emesh/hdl/emesh2packet.v
-read_verilog $top_srcdir/emesh/hdl/packet2emesh.v
-
-#MEMORY/FIFO
-read_verilog $top_srcdir/memory/hdl/fifo_async.v
-read_verilog $top_srcdir/memory/hdl/fifo_sync.v
-read_verilog $top_srcdir/memory/hdl/fifo_cdc.v
-read_verilog $top_srcdir/memory/hdl/memory_dp.v
-read_verilog $top_srcdir/memory/hdl/memory_sp.v
-read_verilog $top_srcdir/memory/hdl/fifo_full_block.v
-read_verilog $top_srcdir/memory/hdl/fifo_empty_block.v
-
-#MMU
-read_verilog $top_srcdir/emmu/hdl/emmu.v
-read_verilog $top_srcdir/emailbox/hdl/emailbox.v
-read_verilog $top_srcdir/edma/hdl/edma.v
-

elink/scripts/xilinx/run.tcl

@@ -1,84 +0,0 @@
-set pwd [file dirname [info script]]
-source $pwd/../../../include/oh.tcl
-
-###########################################################
-#STEP0: Define variables
-set OUTDIR ./tmp
-set PART xc7z010clg400-1
-set TOP axi_elink
-
-file mkdir $OUTDIR
-
-###########################################################
-#STEP1: Read sources, constraints, IP files
-create_project -in_memory -part $PART -force my_project
-source $pwd/read_verilog.tcl
-source $pwd/read_constraints.tcl
-source $pwd/read_ip.tcl
-
-###########################################################
-#STEP2: SYNTHESIS
-###########################################################
-upgrade_ip [get_ips]
-generate_target all [get_ips]
-synth_ip [get_ips]
-synth_design -top $TOP -part $PART
-
-#create a checkpoint
-write_checkpoint -force $OUTDIR/post_syn.dcp
-
-#report timing
-check_timing -verbose -file $OUTDIR/check_timing.rpt
-report_clocks -file $OUTDIR/clock_basic.rpt
-report_clock_interaction -delay_type min_max -significant_digits 3 -file $OUTDIR/clock_cdc.rpt
-report_clock_networks -file $OUTDIR/clock_networks.rpt
-report_timing_summary -file $OUTDIR/post_syn_timing_summary.rpt
-report_utilization -file $OUTDIR/post_syn_util.rpt
-
-###########################################################
-#STEP3: PLACEMENT
-###########################################################
-#optimize design
-opt_design
-
-#place design
-place_design
-
-#optimzier design
-phys_opt_design
-
-#create a checkpoint
-write_checkpoint -force $OUTDIR/post_place.dcp
-
-#post placement repororts
-
-
-report_clock_utilization -file $OUTDIR/clock_util.rpt
-report_utilization -file $OUTDIR/post_place_util.rpt
-report_timing_summary -file $OUTDIR/post_place_timing_summary.rpt
-
-###########################################################
-#STEP4: ROUTING
-###########################################################
-
-#route design
-route_design
-
-#create checkpoint
-write_checkpoint -force $OUTDIR/post_route.dcp
-
-#create reports
-report_route_status -file $OUTDIR/post_route_status.rpt
-report_timing_summary -file $OUTDIR/post_route_timing_summary.rpt
-report_timing -sort_by group -max_paths 100 -path_type summary -file $OUTDIR/post_route_timing.rpt
-report_power -file $OUTDIR/post_route_power.rpt
-report_drc -file $OUTDIR/post_imp_drc.rpt
-
-###########################################################
-#STEP5: GENERATE BITSTREAM AND NETLIST
-###########################################################
-write_verilog -force $OUTDIR/$TOP.v
-
-write_xdc -no_fixed_only -force $OUTDIR/$TOP.xdc
-
-write_bitstream -force $OUTDIR/$TOP.bit