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Moving mailbox registers to new addres

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-Mailbox is a pretty useful little block, registers don't belong in the RX space
-Moved registers to the "MESH" group block at bits [10:8].
-Feel good about this, should not change...
-Has been tested  to work with test/test_regs.emf
-For new register address, see README.md

cc @olajep @peteasa
This commit is contained in:
Andreas Olofsson 2016-01-16 14:44:35 -05:00
parent a1e19e0a5b
commit 240e5b433c
7 changed files with 45 additions and 43 deletions
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24
elink/README.md
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@ -181,26 +181,28 @@ REGISTER | ACCESS | ADDRESS | DESCRIPTION
-----------------|--------|---------|------------------ -----------------|--------|---------|------------------
ELINK_RESET | -W | 0xF0200 | Soft reset ELINK_RESET | -W | 0xF0200 | Soft reset
ELINK_CLK | -W | 0xF0204 | Clock configuration ELINK_CLK | -W | 0xF0204 | Clock configuration
ELINK_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins ELINK_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins
ELINK_VERSION | RW | 0xF020C | Version number (static) ELINK_VERSION | RW | 0xF020C | Version number (static)
*****************|********|*********|************************** *****************|********|*********|**************************
ELINK_TXCFG | RW | 0xF0210 | TX configuration ELINK_TXCFG | RW | 0xF0210 | TX configuration
ELINK_TXSTATUS | RW | 0xF0214 | TX status ELINK_TXSTATUS | RW | 0xF0214 | TX status
ELINK_TXGPIO | RW | 0xF0218 | TX data in GPIO mode ELINK_TXGPIO | RW | 0xF0218 | TX data in GPIO mode
ELINK_TXMONITOR | RW | 0xF021C | TX transaction monitor ELINK_TXMONITOR | RW | 0xF021C | TX transaction monitor
ELINK_TXPACKET | R- | 0xF0220 | TX packet sampler ELINK_TXPACKET | R- | 0xF0220 | TX packet sampler
ELINK_TXMMU | -W | 0xE0000 | TX MMU table
*****************|******* |*********|******************** *****************|******* |*********|********************
ELINK_RXCFG | RW | 0xF0300 | RX configuration ELINK_RXCFG | RW | 0xF0300 | RX configuration
ELINK_RXSTATUS | R- | 0xF0304 | RX status register ELINK_RXSTATUS | R- | 0xF0304 | RX status register
ELINK_RXGPIO | R- | 0xF0308 | RX data in GPIO mode ELINK_RXGPIO | R- | 0xF0308 | RX data in GPIO mode
ELINK_RXOFFSET | RW | 0xF030C | RX mem offset in remap mode ELINK_RXOFFSET | RW | 0xF030C | RX mem offset in remap mode
ELINK_RXDELAY0 | RW | 0xF0310 | RX idelays 4 bit values d[7:0] ELINK_RXDELAY0 | RW | 0xF0310 | RX idelays 4 bit lsb values d[7:0]
ELINK_RXDELAY1 | RW | 0xF0314 | RX idelay msbs and frametap lsbs ELINK_RXDELAY1 | RW | 0xF0314 | RX idelay taps {all msbs,frame lsbs}
ELINK_RXTESTDATA | RW | 0xF0318 | RX sampled data ELINK_RXTESTDATA | RW | 0xF0318 | RX sampled data
ELINK_MAILBOXLO | RW | 0xF0320 | RX mailbox (lower 32 bit) *****************|******* |*********|********************
ELINK_MAILBOXHI | RW | 0xF0324 | RX mailbox (upper 32 bits) ELINK_MAILBOXLO | RW | 0xF0730 | Mailbox (lower 32 bit)
ELINK_MAILBOXSTAT| RW | 0xF0328 | RX mailbox status ELINK_MAILBOXHI | RW | 0xF0734 | Mailbox (upper 32 bits)
ELINK_MAILBOXSTAT| RW | 0xF0738 | Mailbox status
*****************|******* |*********|********************
ELINK_TXMMU | -W | 0xE0000 | TX MMU table
ELINK_RXMMU | -W | 0xE8000 | RX MMU table ELINK_RXMMU | -W | 0xE8000 | RX MMU table
## ELINK_RESET (0xF0200) ## ELINK_RESET (0xF0200)
@ -448,7 +450,7 @@ FIELD | DESCRIPTION
------------------------------- -------------------------------
## ELINK_MAILBOXLO (0xF0320) ## ELINK_MAILBOXLO (0xF0730)
Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Must be read before ELINK_MAILBOXHI is read Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Must be read before ELINK_MAILBOXHI is read
FIELD | DESCRIPTION FIELD | DESCRIPTION
@ -457,14 +459,14 @@ FIELD | DESCRIPTION
------------------------------- -------------------------------
## ELINK_MAILBOXHI (0xF0324) ## ELINK_MAILBOXHI (0xF0734)
Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this register causes the RX FIFO read pointer to increment by one. Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this register causes the RX FIFO read pointer to increment by one.
FIELD | DESCRIPTION FIELD | DESCRIPTION
-------- |--------------------------------------------------- -------- |---------------------------------------------------
[31:0] | Upper data of RX FIFO [31:0] | Upper data of RX FIFO
## ELINK_MAILBOXSTAT (0xF0328) ## ELINK_MAILBOXSTAT (0xF0738)
Status of mailbox Status of mailbox
FIELD | DESCRIPTION FIELD | DESCRIPTION

6
elink/dv/run_axi.sh
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@ -1,7 +1,7 @@
#!/bin/bash #!/bin/bash
if [ -e "test_0.memh" ] if [ -e "test_0.emf" ]
then then
rm test_0.memh rm test_0.emf
fi fi
cp $1 test_0.memh cp $1 test_0.emf
./axi_elink.vvp ./axi_elink.vvp

14
elink/dv/tests/test_regs.emf
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@ -8,9 +8,10 @@ DEADBEEF_00000002_810f0214_05_0000 // (ELINK_TXSTATUS)
DEADBEEF_87654321_810f0218_05_0000 // (ELINK_TXGPIO) DEADBEEF_87654321_810f0218_05_0000 // (ELINK_TXGPIO)
DEADBEEF_AAAAAAAA_810f021C_05_0000 // (ELINK_TXMONITOR) DEADBEEF_AAAAAAAA_810f021C_05_0000 // (ELINK_TXMONITOR)
DEADBEEF_00000000_810f0300_05_0000 // (ELINK_RXCFG) DEADBEEF_00000000_810f0300_05_0000 // (ELINK_RXCFG)
DEADBEEF_00000000_810f0304_05_0000 // (ELINK_RXSTATUS)
DEADBEEF_00000000_810f030C_05_0000 // (ELINK_RXOFFSET) DEADBEEF_00000000_810f030C_05_0000 // (ELINK_RXOFFSET)
DEADBEEF_76543210_810f0310_05_0000 // (ELINK_RXIDELAY0) DEADBEEF_00000000_810f0310_05_0000 // (ELINK_RXIDELAY0)
DEADBEEF_FEDCBA98_810f0314_05_0000 // (ELINK_RXIDELAY1) DEADBEEF_00000000_810f0314_05_0000 // (ELINK_RXIDELAY1)
DEADBEEF_76543210_810f0318_05_0000 // (ELINK_RXTESTDATA) DEADBEEF_76543210_810f0318_05_0000 // (ELINK_RXTESTDATA)
DEADBEEF_11111111_810E0000_05_0000 // (ELINK_TXMMU) DEADBEEF_11111111_810E0000_05_0000 // (ELINK_TXMMU)
DEADBEEF_22222222_810E0004_05_0000 // (ELINK_TXMMU) DEADBEEF_22222222_810E0004_05_0000 // (ELINK_TXMMU)
@ -24,8 +25,9 @@ DEADBEEF_44444444_810E8004_05_0000 // (ELINK_RXMMU)
810D0304_DEADBEEF_810f0304_04_0000 // (ELINK_RXSTATUS) 810D0304_DEADBEEF_810f0304_04_0000 // (ELINK_RXSTATUS)
810D0308_DEADFEEF_810f0308_04_0000 // (ELINK_RXGPIO) 810D0308_DEADFEEF_810f0308_04_0000 // (ELINK_RXGPIO)
fedcba98_76543210_80000000_07_0010 //MBOX (DUMY WRITE FOR DV ENV..) fedcba98_76543210_80000000_07_0010 //MBOX (DUMY WRITE FOR DV ENV..)
810f0310_DEADBEEF_80000000_06_0000 // (E_MAILBOXLO) 810f0730_DEADBEEF_80000000_06_0040 // (E_MAILBOXLO)
810D0318_DEADBEEF_810f0318_04_0000 // (E_MAILBOXSTATUS-READ) 810D0000_DEADBEEF_810f0738_04_0000 // (E_MAILBOXSTATUS-READ)
810D0310_DEADBEEF_810f0310_04_0000 // (E_MAILBOXLO-READ) 810D0004_DEADBEEF_810f0730_04_0000 // (E_MAILBOXLO-READ)
810D0314_DEADFEEF_810f0314_04_0000 // (E_MAILBOXHI_READ) 810D0008_DEADFEEF_810f0734_04_0000 // (E_MAILBOXHI_READ)

16
elink/hdl/elink_regmap.v
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@ -17,9 +17,13 @@
`define EGROUP_RR 4'hD // read response block `define EGROUP_RR 4'hD // read response block
//Register blocks[10:8] //Register blocks[10:8]
`define EGROUP_TX 3'd2 //0200 `define EGROUP_RF 3'd0 //0x000
`define EGROUP_RX 3'd3 //0300 `define EGROUP_TX 3'd2 //0x200
`define EGROUP_DMA 3'd5 //0500 `define EGROUP_RX 3'd3 //0x300
`define EGROUP_CORE 3'd4 //0x400
`define EGROUP_DMA 3'd5 //0x500
`define EGROUP_MEM 3'd6 //0x600
`define EGROUP_MESH 3'd7 //0x700
//ETX-REGS //ETX-REGS
`define E_RESET 6'd0 //F0200-reset `define E_RESET 6'd0 //F0200-reset
@ -43,9 +47,9 @@
//MAILBOX REGS //MAILBOX REGS
`ifndef E_MAILBOXLO `ifndef E_MAILBOXLO
`define E_MAILBOXLO 6'd8 //F0320-reserved `define E_MAILBOXLO 6'hC //F0730-lower 32 bits of mailbox
`define E_MAILBOXHI 6'd9 //F0324-reserved `define E_MAILBOXHI 6'hD //F0734-upper 32 bits of mailbox
`define E_MAILBOXSTAT 6'd10 //F0328-reserved `define E_MAILBOXSTAT 6'hE //F0738-mailbox status
`endif `endif
//DMA (same numbering as in Epiphany, limit to 4 channels) //DMA (same numbering as in Epiphany, limit to 4 channels)

8
elink/hdl/erx_cfg.v
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@ -109,13 +109,11 @@ module erx_cfg (/*AUTOARG*/
//read/write decode //read/write decode
assign cfg_access = erx_cfg_access & assign cfg_access = erx_cfg_access &
(dstaddr_in[19:16] ==`EGROUP_MMR) & (dstaddr_in[19:16] ==`EGROUP_MMR) &
(dstaddr_in[10:8] ==`EGROUP_RX) & (dstaddr_in[10:8] ==`EGROUP_RX);
~dstaddr_in[5]; //reserveed for mailbox
assign mailbox_access = erx_cfg_access & assign mailbox_access = erx_cfg_access &
(dstaddr_in[19:16] ==`EGROUP_MMR) & (dstaddr_in[19:16] ==`EGROUP_MMR) &
(dstaddr_in[10:8] ==`EGROUP_RX) & (dstaddr_in[10:8] ==`EGROUP_MESH);
dstaddr_in[5];
assign dma_access = erx_cfg_access & assign dma_access = erx_cfg_access &
(dstaddr_in[19:16] ==`EGROUP_MMR) & (dstaddr_in[19:16] ==`EGROUP_MMR) &
@ -246,7 +244,7 @@ module erx_cfg (/*AUTOARG*/
dstaddr_out[31:0] <= ecfg_read ? srcaddr_in[31:0] : dstaddr_in[31:0]; dstaddr_out[31:0] <= ecfg_read ? srcaddr_in[31:0] : dstaddr_in[31:0];
data_out[31:0] <= data_in[31:0]; data_out[31:0] <= data_in[31:0];
srcaddr_out[31:0] <= srcaddr_in[31:0]; srcaddr_out[31:0] <= srcaddr_in[31:0];
rx_sel <= ~ecfg_read; rx_sel <= cfg_access;
dma_sel <= dma_access; dma_sel <= dma_access;
mailbox_sel <= mailbox_access; mailbox_sel <= mailbox_access;
tx_sel <= ecfg_tx_read; tx_sel <= ecfg_tx_read;

3
emailbox/hdl/emailbox.v
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@ -90,7 +90,8 @@ module emailbox (/*AUTOARG*/
assign mailbox_write = emesh_access & assign mailbox_write = emesh_access &
emesh_write & emesh_write &
(emesh_addr[31:20]==ID) & (emesh_addr[31:20]==ID) &
(emesh_addr[19:16]==`EGROUP_MMR) & (emesh_addr[19:16]==`EGROUP_MMR) &
(emesh_addr[10:8] ==`EGROUP_MESH) &
(emesh_addr[RFAW+1:2]==`E_MAILBOXLO); (emesh_addr[RFAW+1:2]==`E_MAILBOXLO);
//########################################### //###########################################

17
emailbox/hdl/emailbox_regmap.v
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@ -2,23 +2,18 @@
`define EMAILBOX_REGMAP_V_ `define EMAILBOX_REGMAP_V_
`ifndef E_MAILBOXLO `ifndef E_MAILBOXLO
`define E_MAILBOXLO 6'd8 `define E_MAILBOXLO 6'hC
`define E_MAILBOXHI 6'hD
`define E_MAILBOXSTAT 6'hE
`endif `endif
`ifndef E_MAILBOXHI
`define E_MAILBOXHI 6'd9
`endif
`ifndef E_MAILBOXSTAT
`define E_MAILBOXSTAT 6'd10
`endif
`ifndef EGROUP_MMR `ifndef EGROUP_MMR
`define EGROUP_MMR 4'hF `define EGROUP_MMR 4'hF
`endif `endif
`ifndef EGROUP_MESH
`define EGROUP_MESH 3'h7
`endif
`endif `endif