From 24d824f080ed6ff360f0e1c620ff8e06e5d61609 Mon Sep 17 00:00:00 2001
From: Andreas Olofsson <andreas@adapteva.com>
Date: Wed, 20 May 2015 15:04:29 -0400
Subject: [PATCH] Fixing read response address -using `define from elink_regmap
 (ie 'D')

---
 elink/hdl/emaxi.v       |  1 -
 elink/hdl/esaxi.v       | 12 +++++++-----
 elink/hdl/etx_arbiter.v |  2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/elink/hdl/emaxi.v b/elink/hdl/emaxi.v
index 55c774f..311eb94 100644
--- a/elink/hdl/emaxi.v
+++ b/elink/hdl/emaxi.v
@@ -453,7 +453,6 @@ module emaxi(/*autoarg*/
        begin
           txrr_access_reg     <= m_axi_rready & m_axi_rvalid;
 	  txrr_access         <= txrr_access_reg;//added pipeline stage for data 
-	 
 	  // steer read data according to size & host address lsbs
 	  //all data needs to be right aligned
 	  //(this is due to the Epiphany right aligning all words)
diff --git a/elink/hdl/esaxi.v b/elink/hdl/esaxi.v
index 1b7f82f..2977c43 100644
--- a/elink/hdl/esaxi.v
+++ b/elink/hdl/esaxi.v
@@ -18,7 +18,7 @@ module esaxi (/*autoarg*/
    parameter [11:0]  ID                  = 12'h810;
    parameter         IDW                 = 12;
    parameter         PW                  = 104;
-   parameter [15:0]  RETURN_ADDR         = {ID,4'hE};
+   parameter [15:0]  RETURN_ADDR         = {ID,`EGROUP_RR};
    parameter         AW                  = 32;
    parameter         DW                  = 32;
    
@@ -211,7 +211,7 @@ module esaxi (/*autoarg*/
      begin
       if(~s_axi_aresetn)  
 	begin
-           s_axi_awready <= 1'b0; //TODO: why not set default as 1?
+           s_axi_awready <= 1'b1; //TODO: why not set default as 1?
            write_active  <= 1'b0;           
 	end 
       else 
@@ -427,9 +427,11 @@ module esaxi (/*autoarg*/
    // -- because elink reads are not generally 
    // -- returned in order, we will only allow
    // -- one at a time.
-   
+
+   //TODO: Fix this nonsense, need to improve performance
+   //Allow up to N outstanding transactions, use ID to match them up
+   //Need to look at txrd_wait signal
    assign txrd_write         = 1'b0;
-   
    always @( posedge s_axi_aclk )
      if (~s_axi_aresetn) 
        begin
@@ -440,7 +442,7 @@ module esaxi (/*autoarg*/
           ractive_reg         <= 1'b0;
           rnext               <= 1'b0;          
       end 
-     else 
+     else
        begin
           ractive_reg         <= read_active;
           rnext               <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;        
diff --git a/elink/hdl/etx_arbiter.v b/elink/hdl/etx_arbiter.v
index 5d3ff1d..a8d19d3 100644
--- a/elink/hdl/etx_arbiter.v
+++ b/elink/hdl/etx_arbiter.v
@@ -168,7 +168,7 @@ module etx_arbiter (/*AUTOARG*/
    assign write_in = etx_mux[1];
 
    always @ (posedge clk)
-     if ((write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
+     if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
        begin
 	  etx_access         <= access_in;
 	  etx_packet[PW-1:0] <= etx_mux[PW-1:0];