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Fixing read response address

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-using `define from elink_regmap (ie 'D')
This commit is contained in:
Andreas Olofsson 2015-05-20 15:04:29 -04:00
parent 7f0f858b92
commit 24d824f080
3 changed files with 8 additions and 7 deletions
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1
elink/hdl/emaxi.v
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@ -453,7 +453,6 @@ module emaxi(/*autoarg*/
begin begin
txrr_access_reg <= m_axi_rready & m_axi_rvalid; txrr_access_reg <= m_axi_rready & m_axi_rvalid;
txrr_access <= txrr_access_reg;//added pipeline stage for data txrr_access <= txrr_access_reg;//added pipeline stage for data
// steer read data according to size & host address lsbs // steer read data according to size & host address lsbs
//all data needs to be right aligned //all data needs to be right aligned
//(this is due to the Epiphany right aligning all words) //(this is due to the Epiphany right aligning all words)

8
elink/hdl/esaxi.v
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@ -18,7 +18,7 @@ module esaxi (/*autoarg*/
parameter [11:0] ID = 12'h810; parameter [11:0] ID = 12'h810;
parameter IDW = 12; parameter IDW = 12;
parameter PW = 104; parameter PW = 104;
parameter [15:0] RETURN_ADDR = {ID,4'hE}; parameter [15:0] RETURN_ADDR = {ID,`EGROUP_RR};
parameter AW = 32; parameter AW = 32;
parameter DW = 32; parameter DW = 32;
@ -211,7 +211,7 @@ module esaxi (/*autoarg*/
begin begin
if(~s_axi_aresetn) if(~s_axi_aresetn)
begin begin
s_axi_awready <= 1'b0; //TODO: why not set default as 1? s_axi_awready <= 1'b1; //TODO: why not set default as 1?
write_active <= 1'b0; write_active <= 1'b0;
end end
else else
@ -428,8 +428,10 @@ module esaxi (/*autoarg*/
// -- returned in order, we will only allow // -- returned in order, we will only allow
// -- one at a time. // -- one at a time.
//TODO: Fix this nonsense, need to improve performance
//Allow up to N outstanding transactions, use ID to match them up
//Need to look at txrd_wait signal
assign txrd_write = 1'b0; assign txrd_write = 1'b0;
always @( posedge s_axi_aclk ) always @( posedge s_axi_aclk )
if (~s_axi_aresetn) if (~s_axi_aresetn)
begin begin

2
elink/hdl/etx_arbiter.v
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@ -168,7 +168,7 @@ module etx_arbiter (/*AUTOARG*/
assign write_in = etx_mux[1]; assign write_in = etx_mux[1];
always @ (posedge clk) always @ (posedge clk)
if ((write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait)) if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
begin begin
etx_access <= access_in; etx_access <= access_in;
etx_packet[PW-1:0] <= etx_mux[PW-1:0]; etx_packet[PW-1:0] <= etx_mux[PW-1:0];