diff --git a/elink/hdl/ecfg_base.v b/elink/hdl/ecfg_base.v
index 445d829..9f1bf79 100644
--- a/elink/hdl/ecfg_base.v
+++ b/elink/hdl/ecfg_base.v
@@ -19,7 +19,9 @@ module ecfg_base (/*AUTOARG*/
    parameter DEFAULT_COREID  = 12'h808;   // reset value for ecfg_coreid
    parameter DEFAULT_VERSION = 16'h0000;  // reset value for version
    parameter DEFAULT_CLKDIV  = 4'd7;
+   parameter GROUP           = 4'h0;
    
+
    /******************************/
    /*HARDWARE RESET (EXTERNAL)   */
    /******************************/
@@ -68,8 +70,8 @@ module ecfg_base (/*AUTOARG*/
    /*****************************/
 
    //read/write decode
-   assign ecfg_write  = mi_en &  mi_we;
-   assign ecfg_read   = mi_en & ~mi_we;   
+   assign ecfg_write  = mi_en &  mi_we & (mi_addr[19:16]==GROUP);
+   assign ecfg_read   = mi_en & ~mi_we & (mi_addr[19:16]==GROUP);   
 
    //Config write enables
    assign ecfg_reset_write    = ecfg_write & (mi_addr[RFAW+1:2]==`ELRESET);
diff --git a/elink/hdl/ecfg_if.v b/elink/hdl/ecfg_if.v
index a3004a3..5b576f7 100644
--- a/elink/hdl/ecfg_if.v
+++ b/elink/hdl/ecfg_if.v
@@ -15,7 +15,7 @@ module ecfg_if (/*AUTOARG*/
    mi_tx_emmu_dout
    );
 
-   parameter [11:0]  ELINKID             = 12'h800;
+   parameter ID     = 12'h800;
    parameter DW     = 32;
    parameter AW     = 32;
    parameter PW     = 104;
@@ -104,8 +104,8 @@ module ecfg_if (/*AUTOARG*/
    assign mi_clk = txwr_clk;
    
    //Register file access (from slave)
-   assign mi_wr = txwr_access & (txwr_dstaddr[31:20]==ELINKID);   
-   assign mi_rd = txrd_access & (txrd_dstaddr[31:20]==ELINKID);
+   assign mi_wr = txwr_access & (txwr_dstaddr[31:20]==ID);   
+   assign mi_rd = txrd_access & (txrd_dstaddr[31:20]==ID);
    
    //Only 32 bit writes supported
    assign mi_we         =  mi_wr;   
diff --git a/elink/hdl/ecfg_rx.v b/elink/hdl/ecfg_rx.v
index 1b2f495..0fd7af0 100644
--- a/elink/hdl/ecfg_rx.v
+++ b/elink/hdl/ecfg_rx.v
@@ -17,6 +17,7 @@ module ecfg_rx (/*AUTOARG*/
    /*Compile Time Parameters     */
    /******************************/
    parameter RFAW            = 5;         // 32 registers for now
+   parameter GROUP           = 4'h0;
    
    /******************************/
    /*HARDWARE RESET (EXTERNAL)   */
@@ -61,13 +62,12 @@ module ecfg_rx (/*AUTOARG*/
    /*****************************/
 
    //read/write decode
-   assign ecfg_write  = mi_en &  mi_we;
-   assign ecfg_read   = mi_en & ~mi_we;   
+   assign ecfg_write  = mi_en &  mi_we & (mi_addr[19:16]==GROUP);
+   assign ecfg_read   = mi_en & ~mi_we & (mi_addr[19:16]==GROUP);   
 
    //Config write enables
    assign ecfg_rx_write       = ecfg_write & (mi_addr[RFAW+1:2]==`ELRX);
    
-
    //###########################
    //# RXCFG
    //###########################
diff --git a/elink/hdl/ecfg_tx.v b/elink/hdl/ecfg_tx.v
index ed6c1e0..f527fad 100644
--- a/elink/hdl/ecfg_tx.v
+++ b/elink/hdl/ecfg_tx.v
@@ -18,9 +18,7 @@ module ecfg_tx (/*AUTOARG*/
    /*Compile Time Parameters     */
    /******************************/
    parameter RFAW            = 5;         // 32 registers for now
-   parameter DEFAULT_COREID  = 12'h808;   // reset value for ecfg_coreid
-   parameter DEFAULT_VERSION = 16'h0000;  // reset value for version
-   parameter DEFAULT_CLKDIV  = 4'd7;
+   parameter GROUP           = 4'h0;
    
    /******************************/
    /*HARDWARE RESET (EXTERNAL)   */
@@ -69,8 +67,8 @@ module ecfg_tx (/*AUTOARG*/
    /*****************************/
 
    //read/write decode
-   assign ecfg_write  = mi_en &  mi_we;
-   assign ecfg_read   = mi_en & ~mi_we;   
+   assign ecfg_write  = mi_en &  mi_we & (mi_addr[19:16]==GROUP);
+   assign ecfg_read   = mi_en & ~mi_we & (mi_addr[19:16]==GROUP);   
 
    //Config write enables
    assign ecfg_tx_write       = ecfg_write & (mi_addr[RFAW+1:2]==`ELTX);
diff --git a/elink/hdl/elink.v b/elink/hdl/elink.v
index a236e34..6607940 100644
--- a/elink/hdl/elink.v
+++ b/elink/hdl/elink.v
@@ -268,16 +268,11 @@ module elink(/*AUTOARG*/
    txrr_packet
    );
    
-   parameter DEF_COREID  = 12'h810;
    parameter AW          = 32;
    parameter DW          = 32;
-   parameter IDW         = 12;
-   parameter RFAW        = 13;
-   parameter MW          = 44;
-   parameter INC_PLL     = 1;        //include pll
-   parameter INC_SPI     = 1;        //include spi block
-   parameter ELINKID     = 12'h800;  //elink ID (used for registers)
    parameter PW          = 104;      //packet width   
+   parameter TXID        = 12'h800;  //TX path ID
+   parameter RXID        = 12'h800;  //RX path match ID 
 
    /****************************/
    /*CLK AND RESET             */
@@ -394,7 +389,7 @@ module elink(/*AUTOARG*/
    /***********************************************************/
    /*ELINK CONFIGURATION INTERFACE                            */
    /***********************************************************/
-   defparam ecfg_if.ELINKID=ELINKID;
+   defparam ecfg_if.ID=TXID;
 
    ecfg_if ecfg_if(.rxrr_access		(),//TODO: readback, mux with rr
 		   .rxrr_packet		(),
@@ -430,7 +425,8 @@ module elink(/*AUTOARG*/
                         .clk        (mi_clk),
                       )
    */
-   
+
+   defparam ecfg_base.GROUP=`EGROUP_MMR;
    ecfg_base ecfg_base(
 		       /*AUTOINST*/
 		       // Outputs
@@ -488,7 +484,7 @@ module elink(/*AUTOARG*/
                         );
    */
    
-   
+   defparam erx.ID=RXID;
    erx erx(
 	   /*AUTOINST*/
 	   // Outputs
@@ -538,7 +534,8 @@ module elink(/*AUTOARG*/
                         .emrr_\(.*\)  (emaxi_emrr_\1[]),
                        );
    */
-   
+
+   defparam etx.ID=TXID;
    etx etx(
 	   /*AUTOINST*/
 	   // Outputs
diff --git a/elink/hdl/elink_regmap.v b/elink/hdl/elink_regmap.v
index c797258..3a2e3f5 100644
--- a/elink/hdl/elink_regmap.v
+++ b/elink/hdl/elink_regmap.v
@@ -2,9 +2,10 @@
 //Group set with bits 19:16
 
 //Epiphany Register Memory Map
-`define EGROUP_MMR   4'hE
-`define EGROUP_RXMMU 4'hD
-`define EGROUP_TXMMU 4'hC
+`define EGROUP_MMR     4'hE
+`define EGROUP_RXMMU   4'hD
+`define EGROUP_TXMMU   4'hC
+`define EGROUP_READTAG 4'hB
 
 //ELINK REGISTERS addr[6:2]
 `define ELRESET    5'h0 //E0000