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Refactoring common library

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- Updating interfaces to 2005 style
- Adding license pointers to all files
This commit is contained in:
Andreas Olofsson 2016-04-11 12:01:59 -04:00
parent 5b8328826e
commit 2688bc5aa4
53 changed files with 990 additions and 1534 deletions
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9
src/common/hdl/oh_7seg_decode.v
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@ -1,3 +1,10 @@
//#############################################################################
//# Function: BCD Seven Segment Decoderh #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_7seg_decode ( input [3:0] bcd, //0-9 module oh_7seg_decode ( input [3:0] bcd, //0-9
output a, //a segment (1=0ff) output a, //a segment (1=0ff)
output b, //b segment output b, //b segment
@ -8,7 +15,7 @@ module oh_7seg_decode ( input [3:0] bcd, //0-9
output g //g segment output g //g segment
); );
reg a,b,c,d,e,f,g; reg a,b,c,d,e,f,g;
always @ (*) always @ (*)
case(bcd[3:0]) case(bcd[3:0])

29
src/common/hdl/oh_abs.v
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@ -1,20 +1,17 @@
module oh_abs (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Calculates absolute value of input #
out, overflow, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW = 4;
//inputs
input [DW-1:0] in; //input operand
//outputs
output [DW-1:0] out; //out = abs(in) (signed two's complement)
output overflow; //high for max negative #
module oh_abs #(parameter DW = 2) // data width
(
input [DW-1:0] in, //input operand
output [DW-1:0] out, //out = abs(in) (signed two's complement)
output overflow //high for max negative #
);
assign out[DW-1:0] = in[DW-1] ? ~in[DW-1:0] + 1'b1 : assign out[DW-1:0] = in[DW-1] ? ~in[DW-1:0] + 1'b1 :
in[DW-1:0]; in[DW-1:0];

53
src/common/hdl/oh_add.v
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@ -1,36 +1,24 @@
module oh_add (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Two's compliment adder/subtractor #
sum, cout, zero, neg, overflow, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
a, b, opt_sub, cin //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
module oh_add #(parameter DW = 1 // data width
//############################################################### )
//# Parameters (
//############################################################### input [DW-1:0] a, //first operand
parameter DW = 64; input [DW-1:0] b, //second operand
input opt_sub, //subtraction option
//############################################################### input cin, //carry in
//# Interface output [DW-1:0] sum, //sum output
//############################################################### output cout, //carry output
output zero, //zero flag
//inputs output neg, //negative flag
input [DW-1:0] a; //first operand output overflow //overflow flag
input [DW-1:0] b; //second operand );
input opt_sub; //subtraction option
input cin; //carry in
//outputs
output [DW-1:0] sum; //sum
output cout; //cary out
output zero; //zero flag
output neg; //negative flag
output overflow; //overflow indication
//###############################################################
//# BODY
//###############################################################
wire [DW-1:0] b_sub; wire [DW-1:0] b_sub;
assign b_sub[DW-1:0] = {(DW){opt_sub}} ^ b[DW-1:0]; assign b_sub[DW-1:0] = {(DW){opt_sub}} ^ b[DW-1:0];
@ -39,5 +27,4 @@ module oh_add (/*AUTOARG*/
b_sub[DW-1:0] + b_sub[DW-1:0] +
opt_sub + opt_sub +
cin; cin;
endmodule // oh_add endmodule // oh_add

33
src/common/hdl/oh_arbiter.v
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@ -1,24 +1,17 @@
/* Simple combinatorial priority arbiter //#############################################################################
* bit[0] has highest priority //# Function: Statically configured arbiter #
* //#############################################################################
*/ //# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_arbiter(/*AUTOARG*/ module oh_arbiter #( parameter N = 1,
// Outputs parameter TYPE = "FIXED" // or ROUNDROBIN, FAIR
grants, )
// Inputs (
requests input [N-1:0] requests, //request vector
); output [N-1:0] grants //grant (one hot)
);
parameter N = 99;
parameter TYPE = "FIXED"; //arbiter type
//"FIXED"
//"ROUNDROBIN"
//"FAIR"
input [N-1:0] requests; //request vector
output [N-1:0] grants; //grant (one hot)
wire [N-1:0] waitmask; wire [N-1:0] waitmask;
genvar j; genvar j;

33
src/common/hdl/oh_bin2gray.v
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@ -1,21 +1,17 @@
module oh_bin2gray (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Binary to gray encoder #
gray, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
bin //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
//############################################################### module oh_bin2gray #(parameter DW = 32 // width of data inputs
//# Interface )
//############################################################### (
input [DW-1:0] bin; //binary encoded input input [DW-1:0] bin, //binary encoded input
output [DW-1:0] gray; //gray encoded output output [DW-1:0] gray //gray encoded output
);
parameter DW = 64; //width of converter
//###############################################################
//# BODY
//###############################################################
reg [DW-1:0] gray; reg [DW-1:0] gray;
integer i; integer i;
@ -25,6 +21,5 @@ module oh_bin2gray (/*AUTOARG*/
for (i=0; i<(DW-1); i=i+1) for (i=0; i<(DW-1); i=i+1)
gray[i] = bin[i] ^ bin[i+1]; gray[i] = bin[i] ^ bin[i+1];
end end
endmodule // oh_bin2gray endmodule // oh_bin2gray

28
src/common/hdl/oh_bin2onehot.v Normal file
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@ -0,0 +1,28 @@
//#############################################################################
//# Function: Binary to one hot encoder #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_bin2onehot #(parameter DW = 32) // width of data inputs
(
input [NB-1:0] in, // unsigned binary input
output [DW-1:0] out // one hot output vector
);
localparam NB = $clog2(DW); // encoded bit width
integer i;
reg [DW-1:0] out;
always @*
for(i=0;i<DW;i=i+1)
out[i]=(in[NB-1:0]==i);
endmodule // oh_bin2onehot

26
src/common/hdl/oh_binary_decode.v
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@ -1,26 +0,0 @@
module oh_binary_decode (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter N = 32; // one hot bit width
localparam NB = $clog2(N); // encoded bit width
input [NB-1:0] in;
output [N-1:0] out;
integer i;
reg [N-1:0] out;
always @*
for(i=0;i<N;i=i+1)
out[i]=(in[NB-1:0]==i);
endmodule // oh_binary_decode

23
src/common/hdl/oh_bitreverse.v
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@ -1,14 +1,17 @@
module oh_bitreverse (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Binary to one hot encoder #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW = 64; // width operation module oh_bitreverse #(parameter DW = 32 // width of data inputs
)
input [DW-1:0] in; // data input (
output [DW-1:0] out; // bit reversed output input [DW-1:0] in, // data input
output [DW-1:0] out // bit reversed output
);
reg [DW-1:0] out; reg [DW-1:0] out;
integer i; integer i;

123
src/common/hdl/oh_clockdiv.v
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@ -3,72 +3,78 @@
// Secondary clock must be multiple of first clock # // Secondary clock must be multiple of first clock #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_clockdiv(/*AUTOARG*/ module oh_clockdiv
// Outputs (
clkout0, clkrise0, clkfall0, clkout1, clkrise1, clkfall1, //inputs
// Inputs input clk, // main clock
clk, nreset, clken, clkdiv, clkphase0, clkphase1 input nreset, // async active low reset (from oh_rsync)
); input clkchange, // indicates a parameter change
input clken, // clock enable
//parameters input [7:0] clkdiv, // [7:0]=period (0==bypass, 1=div/2, 2=div/3, etc)
parameter DW = 8; // divider counter width input [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
input [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
//inputs //outputs
input clk; // main clock output clkout0, // primary output clock
input nreset; // async active low reset output clkrise0, // rising edge match
input clken; // clock enable enable output clkfall0, // falling edge match
input [7:0] clkdiv; // [7:0]=period (0==off, 1=div/2, 2=div/3, etc) output clkout1, // secondary output clock
input [15:0] clkphase0; // [7:0]=rising,[15:8]=falling output clkrise1, // rising edge match
input [15:0] clkphase1; // [7:0]=rising,[15:8]=falling output clkfall1, // falling edge match
output clkstable // clock is guaranteed to be stable
//primary clock );
output clkout0; // primary output clock
output clkrise0; // rising edge match
output clkfall0; // falling edge match
//secondary clock
output clkout1; // secondary output clock
output clkrise1; // rising edge match
output clkfall1; // falling edge match
//################################
//# BODY
//################################
//regs //regs
reg [DW-1:0] counter; // free running counter reg [7:0] counter;
reg clkout0_reg; reg clkout0_reg;
reg clkout1_reg; reg clkout1_reg;
reg clkout1_shift; reg clkout1_shift;
reg [2:0] period;
//###########################################
//# CHANGE DETECT (count 8 periods)
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
period[2:0] <= 'b0;
else if (clkchange)
period[2:0] <='b0;
else if(period_match & ~clkstable)
period[2:0] <= period[2:0] +1'b1;
assign clkstable = (period[2:0]==3'b111);
//########################################### //###########################################
//# CYCLE COUNTER //# CYCLE COUNTER
//########################################### //###########################################
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
if (~nreset) if (!nreset)
counter[DW-1:0] <= 'b0; counter[7:0] <= 'b0;
else if(clken) else if(clken)
if(period_match) if(period_match)
counter[DW-1:0] <= 'b0; counter[7:0] <= 'b0;
else else
counter[DW-1:0] <= counter[DW-1:0] + 1'b1; counter[7:0] <= counter[7:0] + 1'b1;
assign period_match = (counter[DW-1:0]==clkdiv[7:0]);
assign period_match = (counter[7:0]==clkdiv[7:0]);
//########################################### //###########################################
//# RISING/FALLING EDGE SELECTORS //# RISING/FALLING EDGE SELECTORS
//########################################### //###########################################
assign clkrise0 = (counter[DW-1:0]==clkphase0[7:0]); assign clkrise0 = (counter[7:0]==clkphase0[7:0]);
assign clkfall0 = (counter[DW-1:0]==clkphase0[15:8]); assign clkfall0 = (counter[7:0]==clkphase0[15:8]);
assign clkrise1 = (counter[DW-1:0]==clkphase1[7:0]); assign clkrise1 = (counter[7:0]==clkphase1[7:0]);
assign clkfall1 = (counter[DW-1:0]==clkphase1[15:8]); assign clkfall1 = (counter[7:0]==clkphase1[15:8]);
//########################################### //###########################################
//# CLKOUT0 //# CLKOUT0
//########################################### //###########################################
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
if(!nreset) if(!nreset)
clkout0_reg <= 1'b0; clkout0_reg <= 1'b0;
@ -78,6 +84,7 @@ module oh_clockdiv(/*AUTOARG*/
clkout0_reg <= 1'b0; clkout0_reg <= 1'b0;
//bypass divider on "divide by 1" //bypass divider on "divide by 1"
//TODO: Fix clock glitch!
assign clkout0 = (clkdiv[7:0]==8'd0) ? clk : // bypass assign clkout0 = (clkdiv[7:0]==8'd0) ? clk : // bypass
clkout0_reg; // all others clkout0_reg; // all others
@ -96,37 +103,13 @@ module oh_clockdiv(/*AUTOARG*/
always @ (negedge clk) always @ (negedge clk)
clkout1_shift <= clkout1_reg; clkout1_shift <= clkout1_reg;
//TODO: Fix clock glitch!
assign clkout1 = (clkdiv[7:0]==8'd0) ? clk : //bypass assign clkout1 = (clkdiv[7:0]==8'd0) ? clk : //bypass
(clkdiv[7:0]==8'd1) ? clkout1_shift : //div2 (clkdiv[7:0]==8'd1) ? clkout1_shift : //div2
clkout1_reg; //all others clkout1_reg; //all others
endmodule // oh_clockdiv endmodule // oh_clockdiv
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////

42
src/common/hdl/oh_clockgate.v
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@ -1,21 +1,18 @@
module oh_clockgate(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Low power clock gate circuit #
eclk, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
nrst, clk, en, se //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW=1; module oh_clockgate #(parameter DW = 1) // width of data
(
input nrst; // active low reset (synced to clk) input nrst, // active low sync reset (synced to input clk)
input clk; // clock input input clk, // clock input
input se; // scan enable input se, // scan enable
input [DW-1:0] en; // enable (from positive edge FF) input [DW-1:0] en, // enable (from positive edge FF)
output [DW-1:0] eclk;// enabled clock output [DW-1:0] eclk// enabled clock output
);
`ifdef CFG_ASIC
`else
wire [DW-1:0] en_sh; wire [DW-1:0] en_sh;
wire [DW-1:0] en_sl; wire [DW-1:0] en_sl;
@ -26,15 +23,14 @@ module oh_clockgate(/*AUTOARG*/
{(DW){~nrst}}; {(DW){~nrst}};
//making signal stable //making signal stable
oh_lat0 #(.DW(1)) lat0 (.out_sh (en_sh[DW-1:0]), oh_lat0 #(.DW(1)) lat0 (.out (en_sh[DW-1:0]),
.in_sl (en_sl[DW-1:0]), .in (en_sl[DW-1:0]),
.clk (clk) .clk (clk)
); );
assign eclk[DW-1:0] = {(DW){clk}} & en_sh[DW-1:0]; assign eclk[DW-1:0] = {(DW){clk}} & en_sh[DW-1:0];
`endif
endmodule // clock_gater endmodule // oh_clockgate

82
src/common/hdl/oh_counter.v
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@ -1,53 +1,30 @@
module oh_counter (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Binary to gray encoder #
count, carry, zero, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
clk, in, en, load, load_data //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
//###############################################################
//# Interface
//###############################################################
parameter DW = 64; module oh_counter #(parameter DW = 32, // width of data inputs
parameter TYPE = "INCREMENT"; //INCREMENT, DECREMENT, GRAY, LFSR parameter TYPE = "INCREMENT" // also DECREMENT, GRAY, LFSR
)
(
input clk, // clk input
input in, // input to count
input en, // enable counter
input load, // load counter
input [DW-1:0] load_data,// load data
output [DW-1:0] count, // current count value
output carry, // carry out from counter
output zero // counter is zero
);
//clock interface // local variables
input clk; // clk input
//counter control
input in; // input to count
input en; // enable counter
input load; // load counter
input [DW-1:0] load_data;// load data
//outputs
output [DW-1:0] count; // current count value
output carry; // carry out from counter
output zero; // counter is zero
//###############################################################
//# Interface
//###############################################################
reg [DW-1:0] count; reg [DW-1:0] count;
reg carry; reg carry;
wire [DW-1:0] count_in; wire [DW-1:0] count_in;
wire carry_in; wire carry_in;
always @(posedge clk)
if(load)
begin
carry <= 1'b0;
count[DW-1:0] <= load_data[DW-1:0];
end
else if (en)
begin
carry <= carry_in;
count[DW-1:0] <= count_in[DW-1:0];
end
assign zero = ~(count[DW-1:0]);
// configure counter based on type // configure counter based on type
generate generate
if(TYPE=="INCREMENT") if(TYPE=="INCREMENT")
@ -69,8 +46,23 @@ module oh_counter (/*AUTOARG*/
$display ("NOT IMPLEMENTED"); $display ("NOT IMPLEMENTED");
end end
endgenerate endgenerate
// counter
always @(posedge clk)
if(load)
begin
carry <= 1'b0;
count[DW-1:0] <= load_data[DW-1:0];
end
else if (en)
begin
carry <= carry_in;
count[DW-1:0] <= count_in[DW-1:0];
end
// counter expired
assign zero = ~(count[DW-1:0]);
endmodule // oh_counter endmodule // oh_counter

39
src/common/hdl/oh_crc.v
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@ -1,28 +1,20 @@
module oh_crc (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: CRC combinatorial encoder wrapper #
crc_state, crc_next, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
data_in //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
//############################################################### module oh_crc #( parameter TYPE = "ETH", // type: "ETH", "OTHER"
//# Interface parameter DW = 8) // width of data
//############################################################### (
input [DW-1:0] data_in, // input data
// parameters input [CW-1:0] crc_state, // input crc state
parameter TYPE = "ETH"; // type: "ETH", "OTHER" output [CW-1:0] crc_next // next crc state
parameter DW = 8; // width of data );
parameter CW = 32; // width of polynomial
// signals
input [DW-1:0] data_in;
output [CW-1:0] crc_state;
output [CW-1:0] crc_next;
//###############################################################
//# BODY
//###############################################################
localparam CW = 32; // width of polynomial
generate generate
if(TYPE=="ETH") if(TYPE=="ETH")
begin begin
@ -45,3 +37,4 @@ module oh_crc (/*AUTOARG*/
endgenerate endgenerate
endmodule // oh_crc endmodule // oh_crc

6
src/common/hdl/oh_csa32.v
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@ -2,11 +2,11 @@
//# Function: Carry Save Adder (3:2) # //# Function: Carry Save Adder (3:2) #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_csa32 #( parameter DW = 1 // data width module oh_csa32 #(parameter DW = 1 // data width
) )
( input [DW-1:0] in0, //input ( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input input [DW-1:0] in1,//input
input [DW-1:0] in2,//input input [DW-1:0] in2,//input

5
src/common/hdl/oh_csa42.v
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@ -2,11 +2,10 @@
//# Function: Carry Save Adder (4:2) # //# Function: Carry Save Adder (4:2) #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_csa42 #( parameter DW = 1 // data width module oh_csa42 #( parameter DW = 1) // data width
)
( input [DW-1:0] in0, //input ( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input input [DW-1:0] in1,//input
input [DW-1:0] in2,//input input [DW-1:0] in2,//input

4
src/common/hdl/oh_csa62.v
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@ -3,10 +3,10 @@
//# Function: Carry Save Adder (6:2) # //# Function: Carry Save Adder (6:2) #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_csa62 #( parameter DW = 1 // data width module oh_csa62 #(parameter DW = 1 // data width
) )
( input [DW-1:0] in0, //input ( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input input [DW-1:0] in1,//input

5
src/common/hdl/oh_csa92.v
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@ -2,11 +2,10 @@
//# Function: Carry Save Adder (9:2) # //# Function: Carry Save Adder (9:2) #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_csa92 #( parameter DW = 1 // data width module oh_csa92 #( parameter DW = 1) // data width
)
( input [DW-1:0] in0, //input ( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input input [DW-1:0] in1,//input

30
src/common/hdl/oh_datagate.v
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@ -1,18 +1,21 @@
module oh_datagate (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Low power data gate #
dout, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
clk, en, din //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW = 32; module oh_datagate #(parameter DW = 32, // width of data inputs
parameter PS = 3; parameter PS = 3 // min quiet time before shutdown
)
(
input clk, // clock
input en, // data valid
input [DW-1:0] din, // data input
output [DW-1:0] dout // data output
);
input clk;
input en;
input [DW-1:0] din;
output [DW-1:0] dout;
reg [PS-1:0] enable_pipe; reg [PS-1:0] enable_pipe;
wire enable; wire enable;
@ -22,6 +25,5 @@ module oh_datagate (/*AUTOARG*/
assign enable = {enable_pipe[PS-1:0],en}; assign enable = {enable_pipe[PS-1:0],en};
assign dout[DW-1:0] = {(DW){enable}} & din[DW-1:0]; assign dout[DW-1:0] = {(DW){enable}} & din[DW-1:0];
endmodule // oh_datagate endmodule // oh_datagate

56
src/common/hdl/oh_debouncer.v
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@ -1,40 +1,35 @@
//######################################################################### //#############################################################################
//# Function: A digital debounce circuit //# Function: A digital debouncer circuit #
//# Usage: Set the BOUNCE and CLKPERIOD values during instantional to suite //#############################################################################
//# your switch and clkperiod. //# Author: Andreas Olofsson #
//# //# License: MIT (see LICENSE file in OH! repository) #
//######################################################################## //#############################################################################
module oh_debouncer (/*AUTOARG*/
// Outputs
clean_out,
// Inputs
clk, nreset, noisy_in
);
// parameters (in milliseconds) module oh_debouncer #( parameter BOUNCE = 100, // bounce time (s)
parameter BOUNCE = 100; // bounce time of switch (s) parameter CLKPERIOD = 0.00001 // period (10ns=0.0001ms)
parameter CLKPERIOD = 0.00001; // period (10ns=0.0001ms)) )
parameter CW = $clog2(BOUNCE/CLKPERIOD);// counter width needed (
input clk, // clock to synchronize to
input nreset, // syncronous active high reset
input noisy_in, // noisy input signal to filter
output clean_out // clean signal to logic
);
// signal interface //################################
input clk; // clock to synchronize to //# wires/regs/ params
input nreset; // syncronous active high reset //################################
input noisy_in; // noisy input signal to filter localparam integer CW = $clog2(BOUNCE/CLKPERIOD);// counter width needed
output clean_out; // clean signal to logic
//regs
//temp variables
wire noisy_synced;
reg noisy_reg; reg noisy_reg;
reg clean_out; reg clean_out;
wire nreset_synced;
// synchronize incoming signal
// synchronize reset
oh_dsync dsync (.dout (noisy_synced), oh_dsync dsync (.dout (noisy_synced),
.clk (clk), .clk (clk),
.din (noisy_in)); .din (noisy_in));
// synchronize input to clk (always!) // synchronize reset to clk
oh_rsync rsync (.nrst_out (nreset_synced), oh_rsync rsync (.nrst_out (nreset_synced),
.clk (clk), .clk (clk),
.nrst_in (nreset)); .nrst_in (nreset));
@ -45,7 +40,7 @@ module oh_debouncer (/*AUTOARG*/
assign change_detected = noisy_reg ^ noisy_synced; assign change_detected = noisy_reg ^ noisy_synced;
// synchronous counter // synchronous counter "filter"
oh_counter #(.DW(CW)) oh_counter #(.DW(CW))
oh_counter (// Outputs oh_counter (// Outputs
.count (), .count (),
@ -64,5 +59,6 @@ module oh_debouncer (/*AUTOARG*/
if(carry) if(carry)
clean_out <= noisy_reg; clean_out <= noisy_reg;
endmodule endmodule // oh_debouncer

47
src/common/hdl/oh_dsync.v
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@ -1,45 +1,34 @@
/* A control signal synchronizer with "PS" number of stages //#############################################################################
*/ //# Function: Clock synchronizer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_dsync (/*AUTOARG*/ module oh_dsync #(parameter DW = 1, // width of data
// Outputs parameter PS = 3 // mnumber of sync stages
dout, )
// Inputs (
clk, din input clk, // clock
); input [DW-1:0] din, // input data
output [DW-1:0] dout // synchronized data
parameter PS = 2; //number of sync pipeline stages );
parameter DW = 1; //number of bits to synchronize
input clk; reg [DW-1:0] sync_pipe[PS-1:0];
input [DW-1:0] din;
output [DW-1:0] dout;
`ifdef TARGET_SIM
reg [DW-1:0] sync_pipe[PS-1:0];
`else
(* ASYNC_REG = "TRUE" *) (* DONT_TOUCH = "TRUE" *) reg [DW-1:0] sync_pipe[PS-1:0];
`endif
genvar i; genvar i;
generate generate
for(i=0;i<PS;i=i+1) for(i=0;i<PS;i=i+1)
if(i==0) if(i==0)
begin always @ (posedge clk)
always @ (posedge clk) sync_pipe[0][DW-1:0] <= din[DW-1:0];
sync_pipe[0][DW-1:0] <= din[DW-1:0];
end
else else
begin
always @ (posedge clk ) always @ (posedge clk )
sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0]; sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0];
end // else: !if(i==0)
endgenerate endgenerate
assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0]; assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0];
endmodule // oh_dsync endmodule // oh_dsync

58
src/common/hdl/oh_edge2pulse.v
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@ -2,32 +2,19 @@
//# Function: Converts an edge to a single cycle pulse # //# Function: Converts an edge to a single cycle pulse #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_edge2pulse(/*AUTOARG*/ module oh_edge2pulse #( parameter DW = 1) // width of data inputs
// Outputs (
out, input clk, // clock
// Inputs input nreset, // async active low reset
clk, nreset, in input [DW-1:0] in, // edge input
); output [DW-1:0] out // one cycle pulse
);
reg [DW-1:0] in_reg;
//########################################
//# INTERFACE
//########################################
parameter DW = 1; // width of data inputs
input clk; // clock
input nreset; // async active low reset
input [DW-1:0] in; // edge input
output [DW-1:0] out; // one cycle pulse
//########################################
//# BODY
//########################################
reg [DW-1:0] in_reg;
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
if(!nreset) if(!nreset)
in_reg[DW-1:0] <= 'b0 ; in_reg[DW-1:0] <= 'b0 ;
@ -37,28 +24,3 @@ module oh_edge2pulse(/*AUTOARG*/
assign out[DW-1:0] = in_reg[DW-1:0] ^ in[DW-1:0] ; assign out[DW-1:0] = in_reg[DW-1:0] ^ in[DW-1:0] ;
endmodule // oh_edge2pulse endmodule // oh_edge2pulse
//////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software")//
// to deal in the Software without restriction, including without limitation//
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT//
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
//////////////////////////////////////////////////////////////////////////////

21
src/common/hdl/oh_edgealign.v
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@ -1,9 +1,11 @@
/* Detects the common aligned positive edge for a //#############################################################################
* slow/fast clocks. The circuit uses the negedge of the fast clock //# Function: Aligns positive edge of slow clock to fast clock #
* to sample the slow clock. Output is positive edge sampled. //# !!!Assumes clocks are aligned and synchronous!!! #
* //#############################################################################
* NOTE: Assumes clocks are aligned and synchronous! //# Author: Andreas Olofsson #
* //# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
/*
* ___________ ___________ * ___________ ___________
* __/ \___________/ \ SLOWCLK * __/ \___________/ \ SLOWCLK
* __ __ __ __ __ __ * __ __ __ __ __ __
@ -16,10 +18,7 @@
* ____ ______ * ____ ______
* \________________/ \________ FIRSTEDGE * \________________/ \________ FIRSTEDGE
* *
*
*
*/ */
module oh_edgealign (/*AUTOARG*/ module oh_edgealign (/*AUTOARG*/
// Outputs // Outputs
firstedge, firstedge,
@ -44,10 +43,6 @@ module oh_edgealign (/*AUTOARG*/
firstedge <= ~clk45 & clk90; firstedge <= ~clk45 & clk90;
end end
//TODO: parametrized based on 1/N ratios?
//TODO: can we do this without using clock as data input?
endmodule // oh_edgealign endmodule // oh_edgealign

59
src/common/hdl/oh_fall2pulse.v
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@ -1,31 +1,18 @@
//############################################################################# //#############################################################################
//# Function: Converts a falling edge to a single cycle pulse # //# Function: Converts a falling edge to a single cycle pulse #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_fall2pulse(/*AUTOARG*/ module oh_fall2pulse #(parameter DW = 1) //data width
// Outputs (
out, input clk, // clock
// Inputs input nreset, // async active low reset
clk, nreset, in input [DW-1:0] in, // edge input
); output [DW-1:0] out // one cycle pulse
);
//########################################
//# INTERFACE
//########################################
parameter DW = 1; // width of data inputs
input clk; // clock
input nreset; // async active low reset
input [DW-1:0] in; // edge input
output [DW-1:0] out; // one cycle pulse
//########################################
//# BODY
//########################################
reg [DW-1:0] in_reg; reg [DW-1:0] in_reg;
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
@ -36,29 +23,5 @@ module oh_fall2pulse(/*AUTOARG*/
assign out[DW-1:0] = ~in[DW-1:0] & in_reg[DW-1:0] ; assign out[DW-1:0] = ~in[DW-1:0] & in_reg[DW-1:0] ;
endmodule // oh_edge2pulse endmodule // oh_fall2pulse
//////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software")//
// to deal in the Software without restriction, including without limitation//
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT//
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
//////////////////////////////////////////////////////////////////////////////

163
src/common/hdl/oh_fifo_async.v
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@ -1,108 +1,73 @@
`include "mio_constants.vh" //#############################################################################
module oh_fifo_async (/*AUTOARG*/ //# Function: Parametrized asynchronous clock FIFO #
// Outputs //#############################################################################
dout, full, prog_full, empty, rd_count, //# Author: Andreas Olofsson #
// Inputs //# License: MIT (see LICENSE file in OH! repository) #
nreset, wr_clk, wr_en, din, rd_clk, rd_en //#############################################################################
);
//##################################################################### module oh_fifo_async # (parameter DW = 104, //FIFO width
//# INTERFACE parameter DEPTH = 32, //FIFO depth (entries)
//##################################################################### parameter TARGET = "GENERIC",//XILINX,ALTERA,GENERIC,ASIC
parameter DW = 104; // FIFO width parameter PROG_FULL = (DEPTH/2),// program full threshold
parameter DEPTH = 32; // FIFO depth (entries) parameter AW = $clog2(DEPTH) // binary read count width
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC )
parameter WAIT = 0; // assert random prog_full wait (
parameter PROG_FULL = DEPTH/2; // program full threshold input nreset, // async reset
parameter AW = $clog2(DEPTH);// binary read count width input wr_clk, // write clock
input wr_en, // write fifo
input [DW-1:0] din, // data to write
input rd_clk, // read clock
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output full, // fifo is full
output prog_full, // fifo reaches full threshold
output empty, // fifo is empty
output [AW-1:0] rd_count // # of valid entries in fifo
);
//clk/reset
input nreset; // async reset
//write port
input wr_clk; // write clock
input wr_en; // write fifo
input [DW-1:0] din; // data to write
//read port
input rd_clk; // read clock
input rd_en; // read fifo
output [DW-1:0] dout; // output data (next cycle)
//status
output full; // fifo is full
output prog_full; // fifo reaches full threshold
output empty; // fifo is empty
output [AW-1:0] rd_count; // valid entries in fifo
//#####################################################################
//# BODY
//#####################################################################
//local wires //local wires
wire fifo_prog_full;
wire wait_random;
wire [AW-1:0] wr_count; // valid entries in fifo wire [AW-1:0] wr_count; // valid entries in fifo
assign prog_full = fifo_prog_full | wait_random;
generate
if(TARGET=="GENERIC") begin : basic
oh_fifo_generic
#(.DEPTH(DEPTH),
.DW(DW))
fifo_generic (
// Outputs
.full (full),
.prog_full (fifo_prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_count (rd_count[AW-1:0]),
.wr_count (wr_count[AW-1:0]),
// Inputs
.nreset (nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else if (TARGET=="XILINX") begin : xilinx
if((DW==104) & (DEPTH==32))
begin
fifo_async_104x32 fifo (
// Outputs
.full (full),
.prog_full (fifo_prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_data_count (rd_count[AW-1:0]),
// Inputs
.rst (~nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end // if ((DW==104) & (DEPTH==32))
end // block: xilinx
endgenerate
//Random wait generator (for testing)
generate generate
if(WAIT>0) if(TARGET=="GENERIC") begin : basic
begin oh_fifo_generic #(.DEPTH(DEPTH),
reg [7:0] wait_counter; .DW(DW))
always @ (posedge wr_clk or negedge nreset) fifo_generic (
if(~nreset) // Outputs
wait_counter[7:0] <= 'b0; .full (full),
else .prog_full (prog_full),
wait_counter[7:0] <= wait_counter+1'b1; .dout (dout[DW-1:0]),
assign wait_random = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0; .empty (empty),
end .rd_count (rd_count[AW-1:0]),
else .wr_count (wr_count[AW-1:0]),
begin // Inputs
assign wait_random = 1'b0; .nreset (nreset),
end // else: !if(WAIT) .wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else if (TARGET=="XILINX") begin : xilinx
if((DW==104) & (DEPTH==32))
begin
fifo_async_104x32
fifo (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_data_count (rd_count[AW-1:0]),
// Inputs
.rst (~nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end // if ((DW==104) & (DEPTH==32))
end // block: xilinx
endgenerate endgenerate
endmodule // oh_fifo_async endmodule // oh_fifo_async

86
src/common/hdl/oh_fifo_cdc.v
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@ -1,57 +1,36 @@
//######################################################################## //#############################################################################
//# FIFO based clock Domain Crosser //# Function: Clock domain crossing FIFO #
//######################################################################## //#############################################################################
module oh_fifo_cdc (/*AUTOARG*/ //# Author: Andreas Olofsson #
// Outputs //# License: MIT (see LICENSE file in OH! repository) #
wait_out, access_out, packet_out, prog_full, full, empty, //#############################################################################
// Inputs
nreset, clk_in, access_in, packet_in, clk_out, wait_in
);
//##################################################################### module oh_fifo_cdc # (parameter DW = 104, //FIFO width
//# INTERFACE parameter DEPTH = 32, //FIFO depth (entries)
//##################################################################### parameter TARGET = "GENERIC" //XILINX,ALTERA,GENERIC,ASIC
parameter DW = 104; // FIFO width )
parameter DEPTH = 32; // FIFO depth (entries) (
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC input nreset, // shared domain async active low reset
parameter WAIT = 0; // assert random prog_full wait input clk_in, // write clock
input access_in, // write access
input [DW-1:0] packet_in, // write packet
output wait_out, // write pushback
input clk_out, //read clock
output access_out, //read access
output [DW-1:0] packet_out, //read packet
input wait_in, // read pushback
output prog_full, // fifo is half full
output full, // fifo is full
output empty // fifo is empty
);
//shared async reset // local variables
input nreset; reg access_out;
//input packet
input clk_in;
input access_in;
input [DW-1:0] packet_in;
output wait_out;
//output packet
input clk_out;
output access_out;
output [DW-1:0] packet_out;
input wait_in;
//status
output prog_full;
output full;
output empty;
//##################################################################### // FIFO control logic
//# BODY
//#####################################################################
//Local wires
wire wr_en;
wire rd_en;
wire empty;
wire full;
wire prog_full;
reg access_out;
//We use the prog_full clean out any buffers in pipe
//Assumption: The "full" state should never be reached!
assign wr_en = access_in; assign wr_en = access_in;
assign rd_en = ~empty & ~wait_in; assign rd_en = ~empty & ~wait_in;
assign wait_out = prog_full; assign wait_out = prog_full; //wait_out should stall access_in signal
//Holds access high while waiting //Holds access high while waiting
always @ (posedge clk_out or negedge nreset) always @ (posedge clk_out or negedge nreset)
@ -63,8 +42,7 @@ module oh_fifo_cdc (/*AUTOARG*/
//Read response fifo (from master) //Read response fifo (from master)
oh_fifo_async #(.TARGET(TARGET), oh_fifo_async #(.TARGET(TARGET),
.DW(DW), .DW(DW),
.DEPTH(DEPTH), .DEPTH(DEPTH))
.WAIT(WAIT))
fifo (.prog_full (prog_full), fifo (.prog_full (prog_full),
.full (full), .full (full),
.rd_count (), .rd_count (),
@ -75,7 +53,7 @@ module oh_fifo_cdc (/*AUTOARG*/
.rd_clk (clk_out), .rd_clk (clk_out),
.wr_en (wr_en), .wr_en (wr_en),
.din (packet_in[DW-1:0]), .din (packet_in[DW-1:0]),
.rd_en (rd_en) .rd_en (rd_en));
);
endmodule // fifo_cdc endmodule // oh_fifo_cdc

79
src/common/hdl/oh_fifo_generic.v
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@ -1,52 +1,32 @@
//##################################################################### //#############################################################################
//# Asynchronous FIFO based on article by Clifford Cummings, //# Function: Generic Async FIFO #
//# "Simulation and Synthesis Techniques for Asynchronous FIFO Design" //# Based on article by Clifford Cummings, #
//# (SNUG2002) // "Simulation and Synthesis Techniques for Asynchronous FIFO Design" #
//# //# (SNUG2002) #
//# Modifications: Using binary comparisons for simplicity. This may cost //#############################################################################
//# a few more gates, but the the clarity is worth it. //# Author: Andreas Olofsson #
//##################################################################### //# License: MIT (see LICENSE file in OH! repository) #
module oh_fifo_generic //#############################################################################
(/*AUTOARG*/
// Outputs
dout, empty, full, prog_full, rd_count, wr_count,
// Inputs
nreset, wr_clk, wr_en, din, rd_clk, rd_en
);
//##################################################################### module oh_fifo_generic #(parameter DW = 104, //FIFO width
//# INTERFACE parameter DEPTH = 32, //FIFO depth (entries)
//##################################################################### parameter PROG_FULL = (DEPTH/2),//program full threshold
parameter AW = $clog2(DEPTH) // binary read count width
// parameters )
parameter DW = 104; // FIFO width (
parameter DEPTH = 16; // FIFO depth (entries) input nreset, // asynch active low reset
parameter PROG_FULL = DEPTH/2; // FIFO full threshold input wr_clk, // write clock
parameter AW = $clog2(DEPTH); // FIFO address width (for model) input wr_en, // write enable
input [DW-1:0] din, // write data
// common reset input rd_clk, // read clock
input nreset; // asynch active low reset input rd_en, // read enable
output [DW-1:0] dout, // read data
// fifo write output empty, // fifo is empty
input wr_clk; // write clock output full, // fifo is full
input wr_en; // write enable output prog_full, // fifo is "half empty"
input [DW-1:0] din; // write data output [AW-1:0] rd_count, // NOT IMPLEMENTED
output [AW-1:0] wr_count // NOT IMPLEMENTED
// fifo read );
input rd_clk; // read clock
input rd_en; // read enable
output [DW-1:0] dout; // read data
// status
output empty; // fifo is empty
output full; // fifo is full
output prog_full; // fifo is "half empty"
output [AW-1:0] rd_count; // NOT IMPLEMENTED
output [AW-1:0] wr_count; // NOT IMPLEMENTED
//#####################################################################
//# BODY
//#####################################################################
//regs //regs
reg [AW:0] wr_addr; // extra bit for wraparound comparison reg [AW:0] wr_addr; // extra bit for wraparound comparison
@ -63,7 +43,7 @@ module oh_fifo_generic
//# Full/empty indicators //# Full/empty indicators
//########################### //###########################
// uses on extra bit for compare to track wraparound pointers // uses one extra bit for compare to track wraparound pointers
// careful clock synchronization done using gray codes // careful clock synchronization done using gray codes
// could get rid of gray2bin for rd_addr_sync... // could get rid of gray2bin for rd_addr_sync...
@ -128,7 +108,6 @@ module oh_fifo_generic
rd_g2b (.bin (rd_addr_sync[AW:0]), rd_g2b (.bin (rd_addr_sync[AW:0]),
.gray (rd_addr_gray_sync[AW:0])); .gray (rd_addr_gray_sync[AW:0]));
//########################### //###########################
//#dual ported memory //#dual ported memory
//########################### //###########################

72
src/common/hdl/oh_fifo_sync.v
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@ -1,40 +1,28 @@
module oh_fifo_sync (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Synchronous FIFO #
dout, full, prog_full, empty, rd_count, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
clk, nreset, din, wr_en, rd_en //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
//#####################################################################
//# INTERFACE
//#####################################################################
parameter DEPTH = 4;
parameter DW = 104;
parameter PROG_FULL = DEPTH/2;
parameter AW = $clog2(DEPTH);
//clk/reset module oh_fifo_sync #(parameter DW = 104, //FIFO width
input clk; // clock parameter DEPTH = 32, //FIFO depth
input nreset; // active high async reset parameter PROG_FULL = (DEPTH/2),//prog_full threshold
parameter AW = $clog2(DEPTH) //rd_count width
//write port )
input [DW-1:0] din; // data to write (
input wr_en; // write fifo input clk, // clock
input nreset, // active high async reset
//read port input [DW-1:0] din, // data to write
input rd_en; // read fifo input wr_en, // write fifo
output [DW-1:0] dout; // output data (next cycle) input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
//Status output full, // fifo full
output full; // fifo full output prog_full, // fifo is almost full
output prog_full; // fifo is almost full output empty, // fifo is empty
output empty; // fifo is empty output [AW-1:0] rd_count // valid entries in fifo
output [AW-1:0] rd_count; // valid entries in fifo );
//#####################################################################
//# BODY
//#####################################################################
reg [AW-1:0] wr_addr; reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr; reg [AW-1:0] rd_addr;
reg [AW-1:0] rd_count; reg [AW-1:0] rd_count;
@ -72,8 +60,7 @@ module oh_fifo_sync (/*AUTOARG*/
oh_memory_dp oh_memory_dp
#(.DW(DW), #(.DW(DW),
.AW(AW)) .AW(AW))
mem ( mem (// read port
// read port
.rd_dout (dout[DW-1:0]), .rd_dout (dout[DW-1:0]),
.rd_clk (clk), .rd_clk (clk),
.rd_en (fifo_read), .rd_en (fifo_read),
@ -83,11 +70,6 @@ module oh_fifo_sync (/*AUTOARG*/
.wr_en (fifo_write), .wr_en (fifo_write),
.wr_wem ({(DW){1'b1}}), .wr_wem ({(DW){1'b1}}),
.wr_addr (wr_addr[AW-1:0]), .wr_addr (wr_addr[AW-1:0]),
.wr_din (din[DW-1:0]) .wr_din (din[DW-1:0]));
);
endmodule // fifo_sync endmodule // oh_fifo_sync
// Local Variables:
// verilog-library-directories:(".")
// End:

30
src/common/hdl/oh_gray2bin.v
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@ -1,23 +1,17 @@
module oh_gray2bin (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Gray to binary encoder #
bin, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
gray //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
//############################################################### module oh_gray2bin #(parameter DW = 32) // width of data inputs
//# Interface (
//############################################################### input [DW-1:0] gray,//gray encoded input
output [DW-1:0] bin //binary encoded output
input [DW-1:0] gray; //gray encoded input );
output [DW-1:0] bin; //binary encoded output
parameter DW = 64; //width of converter
//############################################################### reg [DW-1:0] bin;
//# BODY
//###############################################################
reg [DW-1:0] bin;
integer i,j; integer i,j;
always @* always @*

41
src/common/hdl/oh_iddr.v
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@ -1,30 +1,19 @@
//################################################################## //#############################################################################
//# ***DUAL DATA RATE INPUT*** //# Function: Dual data rate input buffer #
//# //#############################################################################
//# * Equivalent to "SAME_EDGE_PIPELINED" for xilinx //# Author: Andreas Olofsson #
//# * din sampled on rising edge of clk //# License: MIT (see LICENSE file in OH! repository) #
//# * din sampled on falling edge of clk //#############################################################################
//# * q1 holds rising edge data
//# * q2 holds falling edge data
//#
//##################################################################
module oh_iddr (/*AUTOARG*/ module oh_iddr #(parameter DW = 1 // width of data inputs
// Outputs )
q1, q2, (
// Inputs input clk, // clock
clk, ce, din input ce, // clock enable, set to high to clock in data
); input [DW-1:0] din, // data input sampled on both edges of clock
output [DW-1:0] q1, // iddr rising edge sampled data
//parameters output [DW-1:0] q2 // iddr falling edge sampled data
parameter DW = 32; // width of interface );
//interface
input clk; // clock
input ce; // clock enable, set to high to clock in data
input [DW-1:0] din; // data input
output [DW-1:0] q1; // iddr rising edge sampled data
output [DW-1:0] q2; // iddr falling edge sampled data
//regs("sl"=stable low, "sh"=stable high) //regs("sl"=stable low, "sh"=stable high)
reg [DW-1:0] q1_sl; reg [DW-1:0] q1_sl;

71
src/common/hdl/oh_memory_dp.v
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@ -1,50 +1,53 @@
//#############################################################################
//# Function: Dual Port Memory #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
/*########################################################################### module oh_memory_dp # (parameter DW = 104, //memory width
# Function: Dual port memory wrapper (one read/ one write port) parameter DEPTH = 32, //memory depth
# To run without hardware platform dependancy, `define: parameter PROJ = "", //project name
# "TARGET_CLEAN" parameter MCW = 8 //repair/config vector width
############################################################################ )
*/ (//write interface
input wr_clk, //write clock
module oh_memory_dp(/*AUTOARG*/ input wr_en, //write enable
// Outputs input [DW-1:0] wr_wem, //per bit write enable
rd_dout, input [AW-1:0] wr_addr,//write address
// Inputs input [DW-1:0] wr_din, //write data
wr_clk, wr_en, wr_wem, wr_addr, wr_din, rd_clk, rd_en, rd_addr //read interface
); input rd_clk, //read clock
input rd_en, //read enable
parameter AW = 14; //address width input [AW-1:0] rd_addr,//read address
parameter DW = 32; //memory width output [DW-1:0] rd_dout,//read output data
localparam MD = 1<<AW;//memory depth //asic stuff
input vss, // common ground
//write-port input vdd, // periphery power rail
input wr_clk; //write clock input vddm, // sram array power rail
input wr_en; //write enable input shutdown, // shutdown signal from always on domain
input [DW-1:0] wr_wem; //per bit write enable input [MCW-1:0] memconfig, // generic memory config
input [AW-1:0] wr_addr;//write address input [MCW-1:0] memrepair // repair vector
input [DW-1:0] wr_din; //write data );
//read-port
input rd_clk; //read clock
input rd_en; //read enable
input [AW-1:0] rd_addr;//read address
output[DW-1:0] rd_dout;//read output data
reg [DW-1:0] ram [MD-1:0]; localparam AW = $clog2(DEPTH); // address bus width
reg [DW-1:0] ram [DEPTH-1:0];
reg [DW-1:0] rd_dout; reg [DW-1:0] rd_dout;
integer i; integer i;
//read port //registered read port
always @ (posedge rd_clk) always @ (posedge rd_clk)
if(rd_en) if(rd_en)
rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]]; rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
//write port //write port with vector enable
always @(posedge wr_clk) always @(posedge wr_clk)
for (i=0;i<DW;i=i+1) for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i]) if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i]; ram[wr_addr[AW-1:0]][i] <= wr_din[i];
endmodule // memory_dp endmodule // oh_memory_dp

74
src/common/hdl/oh_memory_sp.v
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@ -1,42 +1,40 @@
module oh_memory_sp(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Sinle Port Memory #
dout, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
clk, en, we, wem, addr, din, vss, vdd, vddm, shutdown, memconfig, //# License: MIT (see LICENSE file in OH! repository) #
memrepair, bist_en, bist_we, bist_wem, bist_addr, bist_din //#############################################################################
);
module oh_memory_sp # (parameter DW = 104, //memory width
parameter DEPTH = 32, //memory depth
parameter PROJ = "", //project name
parameter MCW = 8 //repair/config vector width
)
(// memory interface
input clk, // clock
input en, // memory access
input we, // write enable global signal
input [DW-1:0] wem, // write enable vector
input [AW-1:0] addr, // address
input [DW-1:0] din, // data input
output [DW-1:0] dout, // data output
// Power/repair (ASIC)
input vss, // common ground
input vdd, // periphery power rail
input vddm, // sram array power rail
input shutdown, // shutdown signal from always on domain
input [MCW-1:0] memconfig, // generic memory config
input [MCW-1:0] memrepair, // repair vector
// BIST interface (ASICs)
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din // data input
);
// parameters
parameter DW = 32; // memory width
parameter DEPTH = 14; // memory depth
parameter MCW = 8; // repair/config vector width
parameter PROJ = ""; // project name (used for IP selection)
localparam AW = $clog2(DEPTH); // address bus width localparam AW = $clog2(DEPTH); // address bus width
// standard memory interface
input clk; // clock
input en; // memory access
input we; // write enable global signal
input [DW-1:0] wem; // write enable vector
input [AW-1:0] addr; // address
input [DW-1:0] din; // data input
output [DW-1:0] dout; // data output
// Power/repair interface (ASICs only)
input vss; // common ground
input vdd; // periphery power rail
input vddm; // array power rail
input shutdown; // shutdown signal from always on domain
input [MCW-1:0] memconfig; // generic memory config
input [MCW-1:0] memrepair; // repair vector
// BIST interface (ASICs only)
input bist_en; // bist enable
input bist_we; // write enable global signal
input [DW-1:0] bist_wem; // write enable vector
input [AW-1:0] bist_addr; // address
input [DW-1:0] bist_din; // data input
`ifdef CFG_ASIC `ifdef CFG_ASIC
//Actual IP hidden behind wrapper to protect the innocent //Actual IP hidden behind wrapper to protect the innocent
@ -69,7 +67,7 @@ module oh_memory_sp(/*AUTOARG*/
`else `else
//Assume FPGA tool knows what it's doing (single clock...) //Assume FPGA tool knows what it's doing (single clock...)
//Note: shutdown not modeleled properly, should invalidate all entries //Note: shutdown not modeled properly, should invalidate all entries
//Retention should depend on vdd as well //Retention should depend on vdd as well
reg [DW-1:0] ram [DEPTH-1:0]; reg [DW-1:0] ram [DEPTH-1:0];

38
src/common/hdl/oh_mux.v
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@ -1,30 +1,21 @@
//######################################################################### //#############################################################################
//# GENERIC "ONE HOT" N:1 MUX //# Function: "ONE HOT" N:1 MUX #
//# See also oh_mux2.v, oh_mux3.v, etc //#############################################################################
//######################################################################### //# Author: Andreas Olofsson #
module oh_mux (/*AUTOARG*/ //# License: MIT (see LICENSE file in OH! repository) #
// Outputs //#############################################################################
out,
// Inputs
sel, in
);
//#####################################################################
//# INTERFACE
//#####################################################################
parameter DW = 1; // width of data inputs
parameter N = 1; // number of inputs
input [N-1:0] sel; // select vector module oh_mux #( parameter DW = 1, // width of data inputs
input [N*DW-1:0] in; // concatenated input {..,in1[DW-1:0],in0[DW-1:0] parameter N = 1 // number of inputs
output [DW-1:0] out; // output )
(
input [N-1:0] sel, // select vector
input [N*DW-1:0] in, // concatenated input {..,in1[DW-1:0],in0[DW-1:0]
output [DW-1:0] out // output
);
//#####################################################################
//# BODY
//#####################################################################
reg [DW-1:0] out; reg [DW-1:0] out;
//parametrized mux
integer i; integer i;
always @* always @*
begin begin
@ -36,3 +27,4 @@ module oh_mux (/*AUTOARG*/
endmodule // oh_mux endmodule // oh_mux

79
src/common/hdl/oh_mux12.v
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@ -1,45 +1,39 @@
module oh_mux12(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 12:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in11, in10, in9, in8, in7, in6, in5, in4, in3, in2, in1, in0, //# License: MIT (see LICENSE file in OH! repository) #
sel11, sel10, sel9, sel8, sel7, sel6, sel5, sel4, sel3, sel2, sel1, //#############################################################################
sel0
);
parameter DW=1; module oh_mux12 #(parameter DW = 1 ) // width of mux
(
//data inputs input sel11,
input [DW-1:0] in11; input sel10,
input [DW-1:0] in10; input sel9,
input [DW-1:0] in9; input sel8,
input [DW-1:0] in8; input sel7,
input [DW-1:0] in7; input sel6,
input [DW-1:0] in6; input sel5,
input [DW-1:0] in5; input sel4,
input [DW-1:0] in4; input sel3,
input [DW-1:0] in3; input sel2,
input [DW-1:0] in2; input sel1,
input [DW-1:0] in1; input sel0,
input [DW-1:0] in0; input [DW-1:0] in11,
input [DW-1:0] in10,
//select inputs input [DW-1:0] in9,
input sel11; input [DW-1:0] in8,
input sel10; input [DW-1:0] in7,
input sel9; input [DW-1:0] in6,
input sel8; input [DW-1:0] in5,
input sel7; input [DW-1:0] in4,
input sel6; input [DW-1:0] in3,
input sel5; input [DW-1:0] in2,
input sel4; input [DW-1:0] in1,
input sel3; input [DW-1:0] in0,
input sel2; output [DW-1:0] out //selected data output
input sel1; );
input sel0;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] | {(DW){sel2}} & in2[DW-1:0] |
@ -52,7 +46,6 @@ module oh_mux12(/*AUTOARG*/
{(DW){sel9}} & in9[DW-1:0] | {(DW){sel9}} & in9[DW-1:0] |
{(DW){sel10}} & in10[DW-1:0] | {(DW){sel10}} & in10[DW-1:0] |
{(DW){sel11}} & in11[DW-1:0]); {(DW){sel11}} & in11[DW-1:0]);
endmodule // oh_mux12 endmodule // oh_mux12

31
src/common/hdl/oh_mux2.v
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@ -1,21 +1,18 @@
module oh_mux2(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 2:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, sel0, sel1 //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW=1; module oh_mux2 #(parameter DW = 1 ) // width of mux
(
//data inputs input sel1,
input [DW-1:0] in0; input sel0,
input [DW-1:0] in1; input [DW-1:0] in1,
input [DW-1:0] in0,
//select inputs output [DW-1:0] out //selected data output
input sel0; );
input sel1;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0]); {(DW){sel1}} & in1[DW-1:0]);

36
src/common/hdl/oh_mux3.v
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@ -1,24 +1,20 @@
module oh_mux3(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 3:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, sel0, sel1, sel2 //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW=1; module oh_mux3 #(parameter DW = 1 ) // width of mux
(
//data inputs input sel2,
input [DW-1:0] in0; input sel1,
input [DW-1:0] in1; input sel0,
input [DW-1:0] in2; input [DW-1:0] in2,
input [DW-1:0] in1,
//select inputs input [DW-1:0] in0,
input sel0; output [DW-1:0] out //selected data output
input sel1; );
input sel2;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |

52
src/common/hdl/oh_mux4.v
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@ -1,48 +1,38 @@
module oh_mux4(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 4:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, in3, sel0, sel1, sel2, sel3 //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW=1; module oh_mux4 #(parameter DW = 1 ) // width of mux
(
//data inputs input sel3,
input [DW-1:0] in0; input sel2,
input [DW-1:0] in1; input sel1,
input [DW-1:0] in2; input sel0,
input [DW-1:0] in3; input [DW-1:0] in3,
input [DW-1:0] in2,
//select inputs input [DW-1:0] in1,
input sel0; input [DW-1:0] in0,
input sel1; output [DW-1:0] out //selected data output
input sel2; );
input sel3;
output [DW-1:0] out;
wire error;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] | {(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0]); {(DW){sel3}} & in3[DW-1:0]);
`ifdef TARGET_SIM `ifdef TARGET_SIM
wire error;
assign error = (sel0 | sel1 | sel2 | sel3) & assign error = (sel0 | sel1 | sel2 | sel3) &
~(sel0 ^ sel1 ^ sel2 ^ sel3); ~(sel0 ^ sel1 ^ sel2 ^ sel3);
always @ (posedge error) always @ (posedge error)
begin begin
#1 #1 if(error)
if(error)
$display ("ERROR at in oh_mux4 %m at ",$time); $display ("ERROR at in oh_mux4 %m at ",$time);
end end
`endif `endif
endmodule // oh_mux4 endmodule // oh_mux4

47
src/common/hdl/oh_mux5.v
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@ -1,34 +1,29 @@
module oh_mux5(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 5:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, in3, in4, sel0, sel1, sel2, sel3, sel4 //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW=1; module oh_mux5 #(parameter DW = 1 ) // width of mux
(
//data inputs input sel4,
input [DW-1:0] in0; input sel3,
input [DW-1:0] in1; input sel2,
input [DW-1:0] in2; input sel1,
input [DW-1:0] in3; input sel0,
input [DW-1:0] in4; input [DW-1:0] in4,
input [DW-1:0] in3,
//select inputs input [DW-1:0] in2,
input sel0; input [DW-1:0] in1,
input sel1; input [DW-1:0] in0,
input sel2; output [DW-1:0] out //selected data output
input sel3; );
input sel4;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] | {(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0] | {(DW){sel3}} & in3[DW-1:0] |
{(DW){sel4}} & in4[DW-1:0]); {(DW){sel4}} & in4[DW-1:0]);
endmodule // mux5 endmodule // mux5

51
src/common/hdl/oh_mux6.v
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@ -1,32 +1,27 @@
module oh_mux6(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 6:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, in3, in4, in5, sel0, sel1, sel2, sel3, sel4, sel5 //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter DW=1; module oh_mux6 #(parameter DW = 1 ) // width of mux
(
input sel5,
//data inputs input sel4,
input [DW-1:0] in0; input sel3,
input [DW-1:0] in1; input sel2,
input [DW-1:0] in2; input sel1,
input [DW-1:0] in3; input sel0,
input [DW-1:0] in4; input [DW-1:0] in5,
input [DW-1:0] in5; input [DW-1:0] in4,
input [DW-1:0] in3,
//select inputs input [DW-1:0] in2,
input sel0; input [DW-1:0] in1,
input sel1; input [DW-1:0] in0,
input sel2; output [DW-1:0] out //selected data output
input sel3; );
input sel4;
input sel5;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] | {(DW){sel2}} & in2[DW-1:0] |

55
src/common/hdl/oh_mux7.v
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@ -1,35 +1,28 @@
module oh_mux7(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 7:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, in3, in4, in5, in6, sel0, sel1, sel2, sel3, sel4, //# License: MIT (see LICENSE file in OH! repository) #
sel5, sel6 //#############################################################################
);
parameter DW=1; module oh_mux7 #(parameter DW = 1 ) // width of mux
(
input sel6,
//data inputs input sel5,
input [DW-1:0] in0; input sel4,
input [DW-1:0] in1; input sel3,
input [DW-1:0] in2; input sel2,
input [DW-1:0] in3; input sel1,
input [DW-1:0] in4; input sel0,
input [DW-1:0] in5; input [DW-1:0] in6,
input [DW-1:0] in6; input [DW-1:0] in5,
input [DW-1:0] in4,
//select inputs input [DW-1:0] in3,
input sel0; input [DW-1:0] in2,
input sel1; input [DW-1:0] in1,
input sel2; input [DW-1:0] in0,
input sel3; output [DW-1:0] out //selected data output
input sel4; );
input sel5;
input sel6;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |

59
src/common/hdl/oh_mux8.v
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@ -1,37 +1,30 @@
module oh_mux8(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 8:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, in3, in4, in5, in6, in7, sel0, sel1, sel2, sel3, //# License: MIT (see LICENSE file in OH! repository) #
sel4, sel5, sel6, sel7 //#############################################################################
);
parameter DW=1; module oh_mux8 #(parameter DW = 1 ) // width of mux
(
input sel7,
//data inputs input sel6,
input [DW-1:0] in0; input sel5,
input [DW-1:0] in1; input sel4,
input [DW-1:0] in2; input sel3,
input [DW-1:0] in3; input sel2,
input [DW-1:0] in4; input sel1,
input [DW-1:0] in5; input sel0,
input [DW-1:0] in6; input [DW-1:0] in7,
input [DW-1:0] in7; input [DW-1:0] in6,
input [DW-1:0] in5,
//select inputs input [DW-1:0] in4,
input sel0; input [DW-1:0] in3,
input sel1; input [DW-1:0] in2,
input sel2; input [DW-1:0] in1,
input sel3; input [DW-1:0] in0,
input sel4; output [DW-1:0] out //selected data output
input sel5; );
input sel6;
input sel7;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |

64
src/common/hdl/oh_mux9.v
View File

@ -1,38 +1,33 @@
module oh_mux9(/*AUTOARG*/ //#############################################################################
// Outputs //# Function: 9:1 one hot mux #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in0, in1, in2, in3, in4, in5, in6, in7, in8, sel0, sel1, sel2, //# License: MIT (see LICENSE file in OH! repository) #
sel3, sel4, sel5, sel6, sel7, sel8 //#############################################################################
);
parameter DW=1; module oh_mux9 #( parameter DW = 1 ) // width of mux
(
input sel8,
input sel7,
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in8,
input [DW-1:0] in7,
input [DW-1:0] in6,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
//data inputs
input [DW-1:0] in0;
input [DW-1:0] in1;
input [DW-1:0] in2;
input [DW-1:0] in3;
input [DW-1:0] in4;
input [DW-1:0] in5;
input [DW-1:0] in6;
input [DW-1:0] in7;
input [DW-1:0] in8;
//select inputs
input sel0;
input sel1;
input sel2;
input sel3;
input sel4;
input sel5;
input sel6;
input sel7;
input sel8;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] | assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] | {(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] | {(DW){sel2}} & in2[DW-1:0] |
@ -42,7 +37,6 @@ module oh_mux9(/*AUTOARG*/
{(DW){sel6}} & in6[DW-1:0] | {(DW){sel6}} & in6[DW-1:0] |
{(DW){sel7}} & in7[DW-1:0] | {(DW){sel7}} & in7[DW-1:0] |
{(DW){sel8}} & in8[DW-1:0]); {(DW){sel8}} & in8[DW-1:0]);
endmodule // oh_mux9 endmodule // oh_mux9

5
src/common/hdl/oh_oddr.v
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@ -2,11 +2,10 @@
//# Function: Dual data rate output buffer # //# Function: Dual data rate output buffer #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_oddr #(parameter DW = 1 // width of data inputs module oh_oddr #(parameter DW = 1) // width of data inputs
)
( (
input clk, // clock input input clk, // clock input
input [DW-1:0] din1, // data input1 input [DW-1:0] din1, // data input1

101
src/common/hdl/oh_par2ser.v
View File

@ -2,58 +2,36 @@
//# Function: Parallel to Serial Converter # //# Function: Parallel to Serial Converter #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE in OH! repositpory) #
//############################################################################# //#############################################################################
module oh_par2ser (/*AUTOARG*/ module oh_par2ser #(parameter PW = 64, // parallel packet width
// Outputs parameter SW = 1 // serial packet width
dout, access_out, wait_out, )
// Inputs (
clk, nreset, din, load, shift, datasize, lsbfirst, fill, wait_in input clk, // sampling clock
); input nreset, // async active low reset
input [PW-1:0] din, // parallel data
output [SW-1:0] dout, // serial output data
output access_out,// output data valid
input load, // load parallel data (priority)
input shift, // shift data
input [7:0] datasize, // size of data to shift
input lsbfirst, // lsb first order
input fill, // fill bit
input wait_in, // wait input
output wait_out // wait output (wait in | serial wait)
);
// parameters
localparam CW = $clog2(PW/SW); // serialization factor (for counter)
//###########################
//# INTERFACE
//###########################
// parameters
parameter PW = 64; // parallel packet width
parameter SW = 1; // serial packet width
localparam CW = $clog2(PW/SW); // serialization factor (for counter)
// reset, clk
input clk; // sampling clock
input nreset; // async active low reset
// data interface
input [PW-1:0] din; // parallel data
output [SW-1:0] dout; // serial output data
output access_out;// output data valid
// control interface
input load; // load parallel data (priority)
input shift; // shift data
input [7:0] datasize; // size of data to shift
input lsbfirst; // lsb first order
input fill; // fill bit
input wait_in; // wait input
output wait_out; // wait output (wait in | serial wait)
//###########################
//# BODY
//###########################
reg [PW-1:0] shiftreg; reg [PW-1:0] shiftreg;
reg [CW-1:0] count; reg [CW-1:0] count;
//########################## // start serialization
//# STATE MACHINE assign start_transfer = load & ~wait_in & ~busy;
//##########################
assign start_transfer = load &
~wait_in &
~busy;
//transfer counter //transfer counter
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
if(!nreset) if(!nreset)
@ -70,13 +48,9 @@ module oh_par2ser (/*AUTOARG*/
assign access_out = busy; assign access_out = busy;
//wait until valid data is finished //wait until valid data is finished
assign wait_out = wait_in | assign wait_out = wait_in | busy;
busy;
//##########################
//# SHIFT REGISTER
//##########################
// shift register
always @ (posedge clk) always @ (posedge clk)
if(start_transfer) if(start_transfer)
shiftreg[PW-1:0] = din[PW-1:0]; shiftreg[PW-1:0] = din[PW-1:0];
@ -91,29 +65,6 @@ module oh_par2ser (/*AUTOARG*/
endmodule // oh_par2ser endmodule // oh_par2ser
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////

28
src/common/hdl/oh_parity.v
View File

@ -1,17 +1,19 @@
module oh_parity (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Calculates parity value for #
out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
in //# License: MIT (see LICENSE file in OH repository) #
); //#############################################################################
parameter DW = 64; // width of converter module oh_parity #( parameter DW = 2 // data width
)
input [DW-1:0] in; // data input (
output out; // calculated parity bit input [DW-1:0] in, // data input
output out // calculated parity bit
assign parity = ^data[DW-1:0]; );
assign parity = ^in[DW-1:0];
endmodule // oh_parity endmodule // oh_parity

42
src/common/hdl/oh_pll.v
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@ -1,32 +1,26 @@
module oh_pll (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Phase Locked Loop #
clkout, locked, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
clkin, nreset, clkfb, pll_en, clkdiv, clkphase, clkmult //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter N = 16; // number of clock outputs module oh_pll #(parameter N = 8) // number of clocks
( input clkin, // primary clock input
input nreset, // async active low reset
// inputs input clkfb, // feedback clock
input clkin; // primary clock input input pll_en, // enable pll
input nreset; // async active low reset input [N*8-1:0] clkdiv, // clock divider settings (per clock)
input clkfb; // feedback clock input [N*16-1:0] clkphase, // clock phase setting (rise/fall edge)
input pll_en; // enable pll input [7:0] clkmult, // feedback clock multiplier
input [N*8-1:0] clkdiv; // clock divider settings (per clock) output [N-1:0] clkout, // output clocks
input [N*16-1:0] clkphase; // clock phase setting (rise/fall edge) output locked // PLL locked status
input [7:0] clkmult; // feedback clock multiplier );
// outputs
output [N-1:0] clkout; // output clocks
output locked; // PLL locked status
`ifdef TARGET_SIM `ifdef TARGET_SIM
//insert PLL simulation model //insert PLL simulation model
`endif `endif
endmodule // oh_pll endmodule // oh_pll

45
src/common/hdl/oh_pulse2pulse.v
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@ -1,27 +1,22 @@
// FUNCTION: Transfers a pulse on clkin domain to a pulse on clkout domain //#############################################################################
// !!!WARNING: "din" pulse width must be greater than clkout width!!! //# Function: Clock domain one cycle pulse transfer #
// !!"din" pulse width must be 2x greater than clkout width!!! #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pulse2pulse(/*AUTOARG*/ module oh_pulse2pulse (
// Outputs input nrstin, //input domain reset
dout, input din, //input pulse (one clock cycle)
// Inputs input clkin, //input clock
nrstin, din, clkin, nrstout, clkout input nrstout, //output domain reset
); input clkout, //output clock
output dout //output pulse (one clock cycle)
//input clock domain );
input nrstin; //input domain reset
input din; //input pulse (one clock cycle)
input clkin; //input clock
//output clock domain
input nrstout; //output domain reset
input clkout; //output clock
output dout; //output pulse (one clock cycle)
reg toggle_reg; reg toggle_reg;
reg pulse_reg; reg pulse_reg;
wire toggle;
//pulse to toggle //pulse to toggle
assign toggle = din ? ~toggle_reg : toggle_reg; assign toggle = din ? ~toggle_reg : toggle_reg;
@ -31,14 +26,12 @@ module oh_pulse2pulse(/*AUTOARG*/
toggle_reg <= 1'b0; toggle_reg <= 1'b0;
else else
toggle_reg <= toggle; toggle_reg <= toggle;
//metastability synchronizer //metastability synchronizer
oh_dsync #(1) sync(.dout (toggle_sync), oh_dsync #(1) sync(.dout (toggle_sync),
.din (toggle), .din (toggle),
.clk (clkout) .clk (clkout));
);
//toogle to pulse //toogle to pulse
always @ (posedge clkout) always @ (posedge clkout)
if(!nrstout) if(!nrstout)

49
src/common/hdl/oh_pwr_buf.v
View File

@ -2,24 +2,17 @@
//# Function: Buffer that propagates "X" if power supply is invalid # //# Function: Buffer that propagates "X" if power supply is invalid #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_pwr_buf (/*AUTOARG*/ module oh_pwr_buf #( parameter DW = 1) // width of data inputs
// Outputs (
out, input vdd, // supply (set to 1 if valid)
// Inputs input vss, // ground (set to 0 if valid)
vdd, vss, in input [DW-1:0] in, // input signal
); output [DW-1:0] out // buffered output signal
);
parameter DW=1; // width of macro
input vdd; // supply (set to 1 if valid)
input vss; // ground (set to 0 if valid)
input [DW-1:0] in; // input signal
output [DW-1:0] out; // buffered output signal
`ifdef TARGET_SIM `ifdef TARGET_SIM
assign out[DW-1:0] = ((vdd===1'b1) && (vss===1'b0)) ? in[DW-1:0]: assign out[DW-1:0] = ((vdd===1'b1) && (vss===1'b0)) ? in[DW-1:0]:
{(DW){1'bX}}; {(DW){1'bX}};
@ -30,29 +23,5 @@ module oh_pwr_buf (/*AUTOARG*/
endmodule // oh_buf endmodule // oh_pwr_buf
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////

19
src/common/hdl/oh_pwr_gate.v
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@ -1,13 +1,14 @@
module oh_pwr_gate (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Power supply header switch #
vddg, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
npower, vdd //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
input npower; // active low power on module oh_pwr_gate (input npower, // active low power on
input vdd; // input supply input vdd, // input supply
output vddg; // gated supply output vddg // gated output supply
);
`ifdef TARGET_SIM `ifdef TARGET_SIM
assign vddg = ((vdd===1'b1) && (npower===1'b0)) ? 1'b1 : 1'bX; assign vddg = ((vdd===1'b1) && (npower===1'b0)) ? 1'b1 : 1'bX;

51
src/common/hdl/oh_pwr_isolate.v
View File

@ -2,24 +2,18 @@
//# Function: Isolation buffer for multi supply domains # //# Function: Isolation buffer for multi supply domains #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_pwr_isolate (/*AUTOARG*/ module oh_pwr_isolate #(parameter DW = 1) // width of data inputs
// Outputs (
out, input vdd, // supply (set to 1 if valid)
// Inputs input vss, // ground (set to 0 if valid)
vdd, vss, niso, in input niso, // active low isolation signal
); input [DW-1:0] in, // input signal
output [DW-1:0] out // buffered output signal
parameter DW=1; // width of macro );
input vdd; // supply (set to 1 if valid)
input vss; // ground (set to 0 if valid)
input niso; // active low isolation signal
input [DW-1:0] in; // input signal
output [DW-1:0] out; // buffered output signal
`ifdef TARGET_SIM `ifdef TARGET_SIM
assign out[DW-1:0] = ((vdd===1'b1) && (vss===1'b0)) ? ({(DW){niso}} & in[DW-1:0]): assign out[DW-1:0] = ((vdd===1'b1) && (vss===1'b0)) ? ({(DW){niso}} & in[DW-1:0]):
{(DW){1'bX}}; {(DW){1'bX}};
@ -28,28 +22,3 @@ module oh_pwr_isolate (/*AUTOARG*/
`endif `endif
endmodule // oh_buf endmodule // oh_buf
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////

57
src/common/hdl/oh_rise2pulse.v
View File

@ -2,30 +2,17 @@
//# Function: Converts a rising edge to a single cycle pulse # //# Function: Converts a rising edge to a single cycle pulse #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_rise2pulse(/*AUTOARG*/ module oh_rise2pulse #(parameter DW = 1) // data width
// Outputs
out, ( input clk, // clock
// Inputs input nreset, // async active low reset
clk, nreset, in input [DW-1:0] in, // edge input
); output [DW-1:0] out // one cycle pulse
);
//########################################
//# INTERFACE
//########################################
parameter DW = 1; // width of data inputs
input clk; // clock
input nreset; // async active low reset
input [DW-1:0] in; // edge input
output [DW-1:0] out; // one cycle pulse
//########################################
//# BODY
//########################################
reg [DW-1:0] in_reg; reg [DW-1:0] in_reg;
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
@ -36,29 +23,5 @@ module oh_rise2pulse(/*AUTOARG*/
assign out[DW-1:0] = in[DW-1:0] & ~in_reg[DW-1:0] ; assign out[DW-1:0] = in[DW-1:0] & ~in_reg[DW-1:0] ;
endmodule // oh_edge2pulse endmodule // oh_rise2pulse
//////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software")//
// to deal in the Software without restriction, including without limitation//
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT//
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
//////////////////////////////////////////////////////////////////////////////

68
src/common/hdl/oh_ser2par.v
View File

@ -2,40 +2,22 @@
//# Purpose: Serial to Parallel Converter # //# Purpose: Serial to Parallel Converter #
//############################################################################# //#############################################################################
//# Author: Andreas Olofsson # //# Author: Andreas Olofsson #
//# License: MIT (see below) # //# License: MIT (see LICENSE file in OH! repository) #
//############################################################################# //#############################################################################
module oh_ser2par (/*AUTOARG*/ module oh_ser2par #(parameter PW = 64, // parallel packet width
// Outputs parameter SW = 1 // serial packet width
dout, )
// Inputs (
clk, din, lsbfirst, shift input clk, // sampling clock
); input [SW-1:0] din, // serial data
output [PW-1:0] dout, // parallel data
//########################### input lsbfirst, // lsb first order
//# INTERFACE input shift // shift the shifter
//########################### );
// parameters
parameter PW = 64; // parallel packet width
parameter SW = 1; // serial packet width
localparam CW = $clog2(PW/SW); // serialization factor (for counter) localparam CW = $clog2(PW/SW); // serialization factor (for counter)
// reset, clk
input clk; // sampling clock
//data interface
input [SW-1:0] din; // serial data
output [PW-1:0] dout; // parallel data
// control interface
input lsbfirst; // lsb first order
input shift; // shift the shifter
//##############################
//# BODY
//##############################
reg [PW-1:0] dout; reg [PW-1:0] dout;
reg [CW-1:0] count; reg [CW-1:0] count;
wire [PW-1:0] shiftdata; wire [PW-1:0] shiftdata;
@ -47,29 +29,3 @@ module oh_ser2par (/*AUTOARG*/
dout[PW-1:0] <= {dout[PW-SW-1:0],din[SW-1:0]}; dout[PW-1:0] <= {dout[PW-SW-1:0],din[SW-1:0]};
endmodule // oh_ser2par endmodule // oh_ser2par
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////

39
src/common/hdl/oh_shifter.v
View File

@ -1,28 +1,19 @@
module oh_shifter (/*AUTOARG*/ //#############################################################################
// Outputs //# Function: Barrel shifter #
out, zero, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
a, b //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
//############################################################### module oh_shifter #(parameter DW = 1, // data width
//# Parameters parameter TYPE = "LSL"// LSR, SR, LSL
//############################################################### )
parameter DW = 64; (
parameter TYPE = "LSL"; //shift type input [DW-1:0] in, //first operand
//LSL, LSR, or ASR input [DW-1:0] shift,//shift amount
//############################################################### output [DW-1:0] out, // shifted data out
//# Interface output zero //set if all output bits are zero
//############################################################### );
//inputs
input [DW-1:0] a; //first operand
input [DW-1:0] b; //shift amount
//outputs
output [DW-1:0] out;
output zero; //set if all output bits are zero
//TODO: catch shift out?
endmodule // oh_shifter endmodule // oh_shifter

42
src/common/hdl/oh_standby.v
View File

@ -1,28 +1,26 @@
module oh_standby (/*AUTOARG*/ //#############################################################################
// Outputs //# Purpose: Low power standby state machine #
clk_out, //#############################################################################
// Inputs //# Author: Andreas Olofsson #
clk, nreset, wakeup, idle //# License: MIT (see LICENSE file in OH! repository) #
); //#############################################################################
parameter PD = 5; //cycles to stay awake after "wakeup" module oh_standby #( parameter PD = 5) //cycles to stay awake after "wakeup"
(
//Basic Interface input clkin, //clock input
input clk; //clock input input nreset, //sync reset
input nreset; //sync reset input wakeup, //wake up now!
input wakeup; //wake up now! input idle, //core is in idle
input idle; //core is in idle output clkout //clock output
output clk_out; //clock output );
//Wire declarations //Wire declarations
reg [PD-1:0] wakeup_pipe; reg [PD-1:0] wakeup_pipe;
reg idle_reg; reg idle_reg;
wire state_change;
wire clk_en;
// detect an idle state change (wake up on any)
always @ (posedge clk ) always @ (posedge clk )
idle_reg <= idle; idle_reg <= idle;
assign state_change = (idle ^ idle_reg); assign state_change = (idle ^ idle_reg);
always @ (posedge clk) always @ (posedge clk)
@ -36,13 +34,13 @@ module oh_standby (/*AUTOARG*/
~idle; //core not in idle ~idle; //core not in idle
//clock gater (technology specific) //clock gater (technology specific)
oh_clockgate clockgate (.eclk(clk_out), oh_clockgate clockgate (.eclk(clkout),
.clk(clk), .clk(clk),
.en(clk_en), .en(clk_en),
.nrst(nreset), .nrst(nreset),
.se(1'b0) .se(1'b0));
);
endmodule // standby endmodule // oh_standby

39
src/common/hdl/oh_stretcher.v
View File

@ -1,31 +1,22 @@
/* //#############################################################################
* This module stretches a pulse by DW+1 clock cycles //# Purpose: Stretches a pulse by DW+1 clock cycles #
* Can be useful for synchronous clock transfers from fast to slow. //# Adds one cycle latency #
* The block has one cycle latency //#############################################################################
* //# Author: Andreas Olofsson #
* in //# License: MIT (see LICENSE file in OH! repository) #
* clk //#############################################################################
* out
*
*/
module oh_stretcher (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, nrst
);
parameter CYCLES = 4; module oh_stretcher #(parameter CYCLES = 5) // "wakeup" cycles
( input clk, // clock
input in, // input pulse
input nreset, // async active low reset
output out // stretched output pulse
);
input clk;
input in;
input nrst;
output out;
reg [CYCLES-1:0] valid; reg [CYCLES-1:0] valid;
always @ (posedge clk) always @ (posedge clk or negedge nreset)
if(!nrst) if(!nreset)
valid[CYCLES-1:0] <='b0; valid[CYCLES-1:0] <='b0;
else if(in) else if(in)
valid[CYCLES-1:0] <={(CYCLES){1'b1}}; valid[CYCLES-1:0] <={(CYCLES){1'b1}};