Finishing minimal icarus "standardized" testbench

- Driving all values from the command line
- Standardizing around "OH_" to avoid name conflicts
- Driving seed as a parameter value

stdlib/testbench/oh_simctrl.v

@@ -8,8 +8,8 @@
 module oh_simctrl
   #(parameter TIMEOUT         = 5000, // timeout value (cycles)
     parameter PERIOD_CLK      = 10,   // core clock period
-    parameter PERIOD_FASTCLK  = 20,   // fast clock period
+    parameter PERIOD_FASTCLK  = 10,   // fast clock period
-    parameter PERIOD_SLOWCLK  = 20,   // slow clock period
+    parameter PERIOD_SLOWCLK  = 10,   // slow clock period
     parameter RANDOM_CLK       = 0,   // randomize clock
     parameter RANDOM_DATA      = 0    // randomize data
     )

stdlib/testbench/run.sh

@@ -1,13 +1,6 @@
 #!/bin/bash
 
-#ARGUMENTS
-#$1=name of "dut*.bin" to simulate
-#$2=path to test to run
-
-#Uses BASH $RANDOM variable to set seed
-
-rm test_0.emf
-ln -s $2 test_0.emf
-./$1 +SEED=$RANDOM
-
 
+# LFSR
+iverilog -DOH_CTRL="8'h12" -DOH_N=5  sim.v tb_oh_lfsr.v -y ../rtl/ -y . ; ./a.out
+iverilog -DOH_CTRL="8'h9"  -DOH_N=4  sim.v tb_oh_lfsr.v -y ../rtl/ -y . ; ./a.out

stdlib/testbench/sim.v

@@ -25,6 +25,18 @@ module top();
    parameter N  = 32;
 `endif
 
+`ifdef OH_SEED
+   parameter [N-1:0] SEED  = `OH_SEED;
+`else
+   parameter [N-1:0] SEED  = 1;
+`endif
+
+`ifdef OH_CTRL
+   parameter [N-1:0]CTRL  = `OH_CTRL;
+`else
+   parameter [N-1:0] CTRL  = 1;
+`endif
+
 `ifdef OH_CW
    parameter CW  = `OH_CW;
 `else
@@ -85,6 +97,9 @@ module top();
    parameter FILENAME  = "NONE";
 `endif
 
+   wire [N-1:0]	ctrl;			// To testbench of testbench.v
+   wire [N-1:0] seed;			// To testbench of testbench.v
+
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire			clk;			// From oh_simctrl of oh_simctrl.v
@@ -107,11 +122,13 @@ module top();
    // DUT
    //#################################
 
+
+   assign seed[N-1:0] = SEED;
+   assign ctrl[N-1:0] = CTRL;
+
    /*testbench AUTO_TEMPLATE (
     .ext_packet	 ({(PW){1'b0}}),
     .ext_\(.*\)  (1'b0),
-    .ctrl        ({(N){1'b0}}),
-    .seed        ({(PW/4){4'hA}}),
     );
     */
 
@@ -137,8 +154,8 @@ module top();
 	     .fastclk			(fastclk),
 	     .slowclk			(slowclk),
 	     .mode			(mode[2:0]),
-	     .ctrl			({(N){1'b0}}),		 // Templated
+	     .ctrl			(ctrl[N-1:0]),
-	     .seed			({(PW/4){4'hA}}),	 // Templated
+	     .seed			(seed[N-1:0]),
 	     .ext_clk			(1'b0),			 // Templated
 	     .ext_valid			(1'b0),			 // Templated
 	     .ext_packet		({(PW){1'b0}}),		 // Templated

stdlib/testbench/tb_oh_lfsr.v

@@ -21,7 +21,7 @@ module testbench
     input 	    slowclk, //slow clock
     input [2:0]     mode, //0=load,1=go,2=bypass,3=rng
     input [N-1:0]   ctrl, // generic ctrl vector
-    input [PW-1:0]  seed, // seed(s) for rng
+    input [N-1:0]   seed, // seed(s) for rng
     // external write interface
     input 	    ext_clk, //ext packet clock
     input 	    ext_valid, // ext valid signal
@@ -43,76 +43,29 @@ module testbench
    // LOCAL WIRES
    //#################################
 
-   wire dut_active;
-   wire dut_ready;
-   wire dut_error;
-   wire dut_done;
-   wire dut_valid;
-   wire tb_xrandom;
-
    /*AUTOWIRE*/
-   // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire			stim_done;		// From oh_stimulus of oh_stimulus.v
-   wire [PW-1:0]	stim_packet;		// From oh_stimulus of oh_stimulus.v
-   wire			stim_valid;		// From oh_stimulus of oh_stimulus.v
-   // End of automatics
-
    /*AUTOINPUT*/
 
    //#################################
    // DUT LOGIC
    //#################################
 
-   assign dut_active = 1'b1;
    assign dut_ready  = 1'b1;
    assign dut_error  = 1'b0;
    assign dut_done   = 1'b0;
    assign dut_valid  = 1'b0;
    assign dut_clk    = clk;
 
-   /*oh_random AUTO_TEMPLATE (
+   oh_lfsr #(.N(N))
-    .en	    (tb_go),
+   oh_lfsr (// outputs
 	    .out      (dut_status[N-1:0] ),
-    );
+	    // inputs
-    */
+	    .taps     (ctrl[N-1:0]),
-
+	    .seed     (seed[N-1:0]),
-   oh_random #(.N(N))
+	    .en	      (1'b1),
-   oh_random(.mask	({(N){1'b1}}),
-	     .taps	({(N){1'b1}}),
-	     .entaps	(1'b0),
-	     .en	(tb_go),
-	     .seed      ({(N/4){4'hA}}),
-	     /*AUTOINST*/
-	     // Outputs
-	     .out			(dut_status[N-1:0]),	 // Templated
-	     // Inputs
 	    .clk      (clk),
 	    .nreset   (nreset));
 
-   //#################################
-   // STIMULUS
-   //#################################
-
-   oh_stimulus #(.PW(PW),
-		 .CW(CW),
-		 .DEPTH(DEPTH),
-		 .TARGET(TARGET),
-		 .FILENAME(FILENAME))
-   oh_stimulus(/*AUTOINST*/
-	       // Outputs
-	       .stim_valid		(stim_valid),
-	       .stim_packet		(stim_packet[PW-1:0]),
-	       .stim_done		(stim_done),
-	       // Inputs
-	       .nreset			(nreset),
-	       .mode			(mode[1:0]),
-	       .seed			(seed[PW-1:0]),
-	       .ext_clk			(ext_clk),
-	       .ext_valid		(ext_valid),
-	       .ext_packet		(ext_packet[PW-1:0]),
-	       .dut_clk			(dut_clk),
-	       .dut_ready		(dut_ready));
-
 endmodule // tb
 // Local Variables:
 // verilog-library-directories:("." "../rtl")

stdlib/testbench/testbench.v

@@ -20,7 +20,7 @@ module testbench
     input 	    slowclk, //slow clock
     input [2:0]     mode, //0=idle,1=load,2=go,3=rng,4=bypass
     input [N-1:0]   ctrl, // generic ctrl vector
-    input [PW-1:0]  seed, // seed(s) for rng
+    input [N-1:0]  seed, // seed(s) for rng
     // external write interface
     input 	    ext_clk, //ext packet clock
     input 	    ext_valid, // ext valid signal