FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity

Adding DMA source and changing interface

Browse Source 
-DMA added as a master driving out transactions
(this is going to be great!!)
-Changing to packet interface
This commit is contained in:
Andreas Olofsson 2015-04-23 18:03:10 -04:00
parent 842a6d894a
commit 2707541eab
1 changed files with 85 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

162
elink/hdl/erx_disty.v
View File

@ -10,18 +10,18 @@
module erx_disty (/*AUTOARG*/ module erx_disty (/*AUTOARG*/
// Outputs // Outputs
emesh_rd_wait, emesh_wr_wait, emwr_wr_en, emrq_wr_en, emrr_wr_en, rx_rd_wait, rx_wr_wait, edma_wait, rxwr_fifo_access,
erx_write, erx_datamode, erx_ctrlmode, erx_dstaddr, erx_srcaddr, rxwr_fifo_packet, rxrd_fifo_access, rxrd_fifo_packet,
erx_data, rxrr_fifo_access, rxrr_fifo_packet,
// Inputs // Inputs
clk, mmu_en, emmu_access, emmu_write, emmu_datamode, emmu_ctrlmode, clk, mmu_en, emmu_access, emmu_packet, edma_access, edma_packet,
emmu_dstaddr, emmu_srcaddr, emmu_data, emwr_progfull, rxwr_fifo_wait, rxrd_fifo_wait, rxrr_fifo_wait
emrq_progfull, emrr_progfull, ecfg_rx_enable
); );
parameter [11:0] C_READ_TAG_ADDR = 12'h810; parameter [11:0] C_READ_TAG_ADDR = 12'h810;
parameter C_REMAP_BITS = 7; parameter AW = 32;
parameter [31:0] C_REMAP_ADDR = 32'h3E000000; parameter DW = 32;
parameter PW = 104;
// RX clock // RX clock
input clk; input clk;
@ -29,93 +29,101 @@ module erx_disty (/*AUTOARG*/
// MMU enable // MMU enable
input mmu_en; input mmu_en;
//Inputs from MMU //Transaction from MMU
input emmu_access; input emmu_access;
input emmu_write; input [PW-1:0] emmu_packet;
input [1:0] emmu_datamode; output rx_rd_wait;
input [3:0] emmu_ctrlmode; output rx_wr_wait;
input [31:0] emmu_dstaddr;
input [31:0] emmu_srcaddr; //Transaction from DMA
input [31:0] emmu_data; input edma_access;
output emesh_rd_wait; input [PW-1:0] edma_packet;
output emesh_wr_wait; output edma_wait;
// Master FIFO port, writes // Master FIFO port, writes
output emwr_wr_en; output rxwr_fifo_access;
input emwr_progfull; output [PW-1:0] rxwr_fifo_packet;
input rxwr_fifo_wait;
// Master FIFO port, read requests // Master FIFO port, read requests
output emrq_wr_en; output rxrd_fifo_access;
input emrq_progfull; output [PW-1:0] rxrd_fifo_packet;
input rxrd_fifo_wait;
// Master FIFO port, read responses // Master FIFO port, read responses
output emrr_wr_en; output rxrr_fifo_access;
input emrr_progfull; output [PW-1:0] rxrr_fifo_packet;
input rxrr_fifo_wait;
//wires
wire emmu_write;
wire [1:0] emmu_datamode;
wire [3:0] emmu_ctrlmode;
wire [31:0] emmu_dstaddr;
wire [31:0] emmu_srcaddr;
wire [31:0] emmu_data;
//Master Transaction for all FIFOs //regs
output erx_write; reg rxrd_fifo_access;
output [1:0] erx_datamode; reg rxrr_fifo_access;
output [3:0] erx_ctrlmode; reg rxwr_fifo_access;
output [31:0] erx_dstaddr; reg [PW-1:0] rxrd_fifo_packet;
output [31:0] erx_srcaddr; reg [PW-1:0] rxwr_fifo_packet;
output [31:0] erx_data;
// Control bits inputs packet2emesh p2e (// Outputs
input ecfg_rx_enable;//TODO: what to do with this? .access_out (),
.write_out (emmu_write),
//############ .datamode_out (emmu_datamode[1:0]),
//# REGS .ctrlmode_out (emmu_ctrlmode[3:0]),
//############ .dstaddr_out (emmu_dstaddr[AW-1:0]),
.data_out (emmu_data[DW-1:0]),
reg erx_write; .srcaddr_out (emmu_srcaddr[AW-1:0]),
reg [1:0] erx_datamode; // Inputs
reg [3:0] erx_ctrlmode; .packet_in (emmu_packet[PW-1:0])
reg [31:0] erx_dstaddr; );
reg [31:0] erx_srcaddr;
reg [31:0] erx_data; //Read requests (emmu has priority over edma)
assign emmu_read = (emmu_access & ~emmu_write);
reg emwr_wr_en;
reg emrq_wr_en;
reg emrr_wr_en;
//############
//# PIPELINE AND DISTRIBUTE
//############
always @ (posedge clk) always @ (posedge clk)
begin if(emmu_read | edma_access )
erx_write <= emmu_write;
erx_datamode[1:0] <= emmu_datamode[1:0];
erx_ctrlmode[3:0] <= emmu_ctrlmode[3:0];
erx_dstaddr[31:0] <= mmu_en ? emmu_dstaddr[31:0] : {C_REMAP_ADDR[31:(32-C_REMAP_BITS)],
emmu_dstaddr[(31-C_REMAP_BITS):0]};
erx_srcaddr[31:0] <= emmu_srcaddr[31:0];
erx_data[31:0] <= emmu_data[31:0];
end
always @ (posedge clk)
if(emmu_access)
begin begin
emrq_wr_en <= ~emmu_write; rxrd_fifo_access <= 1'b1;
emrr_wr_en <= emmu_write & (emmu_dstaddr[31:20] == C_READ_TAG_ADDR); rxrd_fifo_packet[PW-1:0] <= emmu_read ? emmu_packet[PW-1:0] :
emwr_wr_en <= emmu_write & (emmu_dstaddr[31:20] != C_READ_TAG_ADDR); edma_packet[PW-1:0];
end end
else else
begin begin
emrq_wr_en <= 1'b0; rxrd_fifo_access <= 1'b0;
emrr_wr_en <= 1'b0;
emwr_wr_en <= 1'b0;
end end
//Write and read response from emmu
always @ (posedge clk)
if(emmu_access)
begin
rxwr_fifo_packet[PW-1:0] <= emmu_packet[PW-1:0];
rxrr_fifo_access <= emmu_write & (emmu_dstaddr[31:20] == C_READ_TAG_ADDR);
rxwr_fifo_access <= emmu_write & (emmu_dstaddr[31:20] != C_READ_TAG_ADDR);
end
else
begin
rxrr_fifo_access <= 1'b0;
rxwr_fifo_access <= 1'b0;
end
assign rxrr_fifo_packet[PW-1:0] = rxwr_fifo_packet[PW-1:0];
//############################# //wait signals
//# Wait signal passthroughs assign rx_rd_wait = rxrd_fifo_wait;
//############################# assign rx_wr_wait = rxwr_fifo_wait | rxrr_fifo_wait;
assign edma_wait = rxrd_fifo_wait | emmu_read;
assign emesh_rd_wait = emrq_progfull;
assign emesh_wr_wait = emwr_progfull | emrr_progfull;
endmodule // erx_disty endmodule // erx_disty
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
//#############################################################################
/* /*
This file is part of the Parallella Project. This file is part of the Parallella Project.