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ESAXI cleanup
-widen address bus to 32 bits -blocking access to elink on ecfg access -fixing decoding for embox
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@ -87,7 +87,7 @@ module esaxi (/*autoarg*/
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input s_axi_aresetn;
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//Read address channel
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input [29:0] s_axi_araddr;
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input [31:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input [7:0] s_axi_arlen;
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@ -98,7 +98,7 @@ module esaxi (/*autoarg*/
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input s_axi_arvalid;
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//Write address channel
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input [29:0] s_axi_awaddr;
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input [31:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input [7:0] s_axi_awlen;
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@ -159,14 +159,14 @@ module esaxi (/*autoarg*/
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reg write_active;
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reg b_wait; // waiting to issue write response (unlikely?)
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reg emwr_access;
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reg emwr_access_all;
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reg [3:0] emwr_ctrlmode;
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reg [1:0] emwr_datamode;
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reg [31:0] emwr_dstaddr;
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reg [31:0] emwr_data;
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reg [31:0] emwr_srcaddr; //upper 32 bits in case 64 bit writes are supported
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reg emrq_access;
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reg emrq_access_all;
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reg [3:0] emrq_ctrlmode;
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reg [1:0] emrq_datamode;
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reg [31:0] emrq_dstaddr;
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@ -199,6 +199,7 @@ module esaxi (/*autoarg*/
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//addr_lsb = 3 for 64 bits (n downto 3)
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//TODO? Do we really need this?
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localparam integer addr_lsb = 2;
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wire [11:0] elinkid=ELINKID;
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//###################################################
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//#WRITE ADDRESS CHANNEL
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@ -248,13 +249,9 @@ module esaxi (/*autoarg*/
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begin
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if( s_axi_awready & s_axi_awvalid )
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begin
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//TODO: If we support only one host read, why the need?
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//s_axi_bid <= s_axi_awid;
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//TODO: something is wrong here!!!
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axi_awaddr[31:0] <= { ecfg_coreid[11:c_s_axi_addr_width-20],
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s_axi_awaddr[29:0] };
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axi_awsize <= s_axi_awsize; // 0=byte, 1=16b, 2=32b
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axi_awburst <= s_axi_awburst; // type, 0=fixed, 1=incr, 2=wrap
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axi_awaddr[31:0] <= s_axi_awaddr[31:0];
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axi_awsize <= s_axi_awsize; // 0=byte, 1=16b, 2=32b
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axi_awburst <= s_axi_awburst; // type, 0=fixed, 1=incr, 2=wrap
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end
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else if( s_axi_wvalid & s_axi_wready )
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@ -354,13 +351,12 @@ module esaxi (/*autoarg*/
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begin
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if( s_axi_arready & s_axi_arvalid )
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begin
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//TODO: something is wrong..
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axi_araddr[31:0] <= { ecfg_coreid[11:c_s_axi_addr_width-20],
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s_axi_araddr[29:0] }; // start address of transfer
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axi_arlen <= s_axi_arlen;
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axi_arburst <= s_axi_arburst;
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axi_arsize <= s_axi_arsize;
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s_axi_rlast <= ~(|s_axi_arlen);
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//NOTE: upper 2 bits get chopped by Zynq
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axi_araddr[31:0] <= s_axi_araddr[31:0]; //transfer start address
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axi_arlen <= s_axi_arlen;
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axi_arburst <= s_axi_arburst;
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axi_arsize <= s_axi_arsize;
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s_axi_rlast <= ~(|s_axi_arlen);
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//s_axi_rid <= s_axi_arid;
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end
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else if( s_axi_rvalid & s_axi_rready)
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@ -393,17 +389,17 @@ module esaxi (/*autoarg*/
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emwr_dstaddr_reg[31:0] <= 32'd0;
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emwr_ctrlmode_reg[3:0] <= 4'd0;
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emwr_datamode_reg[1:0] <= 2'd0;
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emwr_access <= 1'b0;
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emwr_access_all <= 1'b0;
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pre_wr_en <= 1'b0;
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end
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else
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begin
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pre_wr_en <= s_axi_wready & s_axi_wvalid;
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emwr_access <= pre_wr_en;
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emwr_access_all <= pre_wr_en;
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emwr_ctrlmode_reg[3:0] <= ecfg_tx_ctrlmode[3:0];//static
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emwr_datamode_reg[1:0] <= axi_awsize[1:0];
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emwr_dstaddr_reg[31:2] <= axi_awaddr[31:2]; //set lsbs of address based on write strobes
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if(s_axi_wstrb[0])
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if(s_axi_wstrb[0] | (axi_awsize[1:0]==2'b10))
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begin
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emwr_data_reg[31:0] <= s_axi_wdata[31:0];
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emwr_dstaddr_reg[1:0] <= 2'd0;
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@ -434,7 +430,6 @@ module esaxi (/*autoarg*/
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emwr_dstaddr[31:0] <= 32'd0;
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emwr_ctrlmode[3:0] <= 4'd0;
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emwr_datamode[1:0] <= 2'd0;
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emwr_access <= 1'b0;
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end
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else
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begin
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@ -444,6 +439,9 @@ module esaxi (/*autoarg*/
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emwr_ctrlmode[3:0] <= emwr_ctrlmode_reg[3:0];
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emwr_datamode[1:0] <= emwr_datamode_reg[1:0];
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end // else: !if(~s_axi_aresetn)
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assign emwr_access=emwr_access_all & ~(emwr_dstaddr[31:20]==elinkid[11:0]);
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//###################################################
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//#READ REQUEST (DATA CHANNEL)
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@ -470,7 +468,7 @@ module esaxi (/*autoarg*/
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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emrq_access <= 1'b0;
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emrq_access_all <= 1'b0;
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emrq_datamode[1:0] <= 2'd0;
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emrq_ctrlmode[3:0] <= 4'd0;
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emrq_dstaddr[31:0] <= 32'd0;
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@ -482,7 +480,7 @@ module esaxi (/*autoarg*/
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begin
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ractive_reg <= read_active; //read request state machone
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rnext <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;
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emrq_access <= ( ~ractive_reg & read_active ) | rnext;
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emrq_access_all <= ( ~ractive_reg & read_active ) | rnext;
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emrq_datamode[1:0] <= axi_arsize[1:0];
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emrq_ctrlmode[3:0] <= ecfg_tx_ctrlmode;
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emrq_dstaddr[31:0] <= axi_araddr[31:0];
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@ -514,18 +512,18 @@ module esaxi (/*autoarg*/
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s_axi_rvalid <= 1'b0;
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end // else: !if( s_axi_aresetn == 1'b0 )
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assign emrq_access=emrq_access_all & ~(emrq_dstaddr[31:20]==elinkid[11:0]);
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//###################################################
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//#Register Inteface Logic
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//###################################################
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assign mi_clk = s_axi_aclk;
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//Register file access (from slave)
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assign mi_wr = emwr_access & (emwr_dstaddr[31:20]==ELINKID);
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assign mi_rd = emrq_access & (emrq_dstaddr[31:20]==ELINKID);
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assign mi_wr = emwr_access_all & (emwr_dstaddr[31:20]==elinkid[11:0]);
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assign mi_rd = emrq_access_all & (emrq_dstaddr[31:20]==elinkid[11:0]);
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//Only 32 bit writes supported
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assign mi_we = mi_wr;
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@ -539,8 +537,9 @@ module esaxi (/*autoarg*/
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assign mi_ecfg_sel = mi_en & (mi_addr[19:16]==`EGROUP_MMR);
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assign mi_rx_emmu_sel = mi_en & (mi_addr[19:16]==`EGROUP_RXMMU);
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assign mi_tx_emmu_sel = mi_en & (mi_addr[19:16]==`EGROUP_TXMMU);
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assign mi_embox_sel = mi_en & (mi_addr[19:16]==`EGROUP_EMBOX);
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assign mi_embox_sel = mi_ecfg_sel & (mi_addr[6:2]==`EMBOXLO |
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mi_addr[6:2]==`EMBOXHI)
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;
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//Data
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assign mi_din[31:0] = emwr_data[31:0];
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@ -550,7 +549,8 @@ module esaxi (/*autoarg*/
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mi_ecfg_reg <= mi_ecfg_sel;
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mi_rx_emmu_reg <= mi_rx_emmu_sel;
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mi_tx_emmu_reg <= mi_tx_emmu_sel;
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mi_embox_reg <= mi_embox_sel;
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//feel hacky, clean up?
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mi_embox_reg <= mi_embox_sel;
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mi_rd_reg <= mi_rd;
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end
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